Other Parts Discussed in Thread: TPS54618
Why the frequency in buck rarely up to 4MHz?
I have a few assumption. If the frequency is too high,
- there will be narrow gap for dead time. Synchronization buck need dead time between upper MOS and lower MOS.
- the Rboot need to be reduced and the voltage in SW will overshoot, which leading to EMI problem.
- Cboot may have not enough time to be charged, making the upper mos inoperative.
- Qg which represents the total amount of charge required by the gate may cannot have enough time to build up. The rising edge may not be so fast.
As to why it was 4 MHz instead of other numbers, I have no conclusion.