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TPS6594-Q1: Max capacitance on LDO output

Henrik Hillberg
Prodigy 10 points
Part Number: TPS6594-Q1
Other Parts Discussed in Thread: TDA4VM

Circuit: TPS65941111RWERQ1 (datasheet SLVSEA7B – DECEMBER 2019 – REVISED FEBRUARY 2022)

 

What does the Output filtering effective capacitance actually mean (LDO1-3, chapter 7.5, row 1.1b, LDO4 chapter 7.6, row 2.1b)? Can you load any of the LDO1-4 outputs with more than 4 uF in any case? What do you then risc? What can happen if you load with say 10-20 uF?

 

When comparing a TI design with the PMIC (TDA4VM Edge AI Kit - DUAL TPS65941x PMICs, PROC112 001 J721EXSKG01EVM, rev A, Monday, October 25, 2021) it looks like for instance the LDO4 of PMIC A is loaded with more than 4 uF. The voltage generated is called VDA_MCU_1V8 and it looks to have at least 2.2 uF +  5*4.7 uF as load. Is that possible (and then why)?

  • 0
    TI__Mastermind 48691 points

    Hello,

      The output cap value is limited by the rail ramp up/down timing (Slew Rate); too slow ramp may cause RVC (Residual Voltage Checking) error. The given max value is referred to its output pin effective value; when considering DCR of PCB trace and other derating of caps, POL (Point Of Load) cap value can be larger than the given max value.

     TI reference design has been validated for the cap value.

    Thanks!

    Phil