Hi Team,
when we follow the power down seqence , what is the PWM state when the VR_EN is removed but the 3.3V is still there?
and what is the PWM state during the 3.3 power off?

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Hi Team,
when we follow the power down seqence , what is the PWM state when the VR_EN is removed but the 3.3V is still there?
and what is the PWM state during the 3.3 power off?

Hello Fanbin,
During both of those conditions, the PWM will go into high impedance mode and tell the power stage to turn off both FETs.
Thanks,
Travis