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UCC12040: Layout question.

Motoyasu Hattori
Genius 11095 points
Part Number: UCC12040

Hi,

My customer has two questions of Layout.  Could you please answer them?

  1. According to 10.2 Layout example on the datasheet, TP1 for VINP is routed under C1 capacitor, and TP3 for VISO is routed under C4 capacitor.  He seems not good pattern on these lines.  Could you please let us know the reason why these are routed under capacitors?   My understanding is priority of TP routing is lower than other lines.  Is it correct?  Please let us know.
  2. On this layout example, routing of #16 GNDS pin is longer than one of #15 GNDS pin.  How long line is routed from #16 GNDS  pin to GND plane?  In other words, How far between #15 GND pin and C3 GND?   Please advise us.

Thanks and best regards,
M.HATTORI.

  • 0
    TI__Mastermind 33115 points

    Hattori-san

    1. You are correct that test points should receive the lowest routing priority and in the case of TP1, I believe the intent was to try and obtain the lowest possible noise at TP1. This is why the TP1 routing trace is coming directly from C2 (100nF HF bypass capacitor) which is the right thing to do but then the trace is routed beneath C1 which I would have preferred not to do. The same comment can also apply to TP3 (C3, C4) on the secondary side.
    2. The GNDS connection to pin 16 includes a "keepout" region I've circled in blue below. Separating pin 16 this way is not necessary and I will plan to remove it in the next revision. When you remove the keepout region, your routing should connect directly into the GNDS plane as shown in the second image below:

    Regards,

    Steve M