Active Clamp Flyback

Hello Jacob, 

Although the current through the clamp capacitor changes direction in region 5, the voltage polarity of the clamp cap does not change because its voltage does not drop significantly.  The voltage on the active clamp cap (not really a snubber) is always close to the reflected voltage (Nps * Vout) on the primary winding. 

The energy in the leakage inductance (Llk) charges Cclamp up a little above Nps*Vout in region 4 and then Cclamp resonates with Llk to discharge a little below Nps*Vout in region 5. 
Additional charge is pulled out of Cclamp in region 6 to establish the required negative current for ZVS.  This charge is replaced into Cclamp by the magnetizing inductance current in region 3 of the next cycle.   

Overall, the average voltage on Cclamp = Nps*Vout and ripple voltage across Cclamp is small compared to Nps*Vout.  
Cclamp rings with Llk based on the voltage difference between the peak of V_Cclamp and the reflected voltage on the primary winding (Nps*Vout).

Regards,

Ulrich

Hello Jacob, 

No need to send the simulation file.  

The schematic pdf shows that you are running the power stage in an open-loop manner.
The on-time of the top-Fet is much longer than it needs to be and it is completely draining the clamp-cap.  
In fact, it is on so long that energy from Cout is reverse charging it to -40V.

The next cycle takes most of the Lm magnetizing current to recharge Cclamp back up to Nps*Vout before it can resonate any of the energy through the leakage inductance out to the secondary.  

From waveform clues, it appears that your turns ratio is 9:1 or 10:1, and since your reflected voltage (135~150V) is almost 4X your input voltage (44V), there is no need to generate any negative current at all to achieve ZVS.  ZVS is automatic when Vreflect > Vbulk.  Therefore the top-Fet Vgs should end almost immediately after the clamp resonance is finished.  

The clamp resonance duration is ~1us, and the peak current on the secondary is ~50mV/5mR = ~10Apk to deliver 15V/50R = 0.3A average load. 
This indicates that the value of the clamp cap appears to be rather low, however I don't know if 0.3A is the maximum load or some light-load condition.  
So, the value may be correct based on some initial design requirement. 

But for this particular line and load condition, switching frequency and top and bottom FET duty cycles are inappropriate for proper ACF operation.   
The UCC28780 and UCC28782 controllers would adjust all the timings appropriately for varying conditions, provided that the component values were set up following the design procedure in the datasheets.  They would shift into the appropriate burst mode if this is a light-load condition.

Even with correct components, open-loop operation requires the user to adjust all of the various control timings as needed each time the line and/or load is changed.  This is not a trivial task, given that the timings of the volt-second balance within a cycle must also accommodate timings for generating negative current and for ZVS ringing.  The switching period shown is about 21us, which is about 47.6kHz.  For a 4.5W load and 200uH inductance, the switching frequency should be much higher, even at only 44V input.  Significant iteration will be needed to find the correct on-times for the bottom and top Fets, and for the appropriate independent delay times between their falling and rising edges, to achieve normal ACF operation.  

Regards,
Ulrich