When testing with a dead battery (2.3V), the measured delay between VBUS rise and VSYS rise is ~760ms.
Why is this delay so long? Any opportunity to decrease this timing?
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When testing with a dead battery (2.3V), the measured delay between VBUS rise and VSYS rise is ~760ms.
Why is this delay so long? Any opportunity to decrease this timing?
Hi Cole,
Since Monday (9/5/22) is a federal holiday, we will get back to you on Tuesday.
Thank you for your understanding.
Regards,
Arelis G. Guerrero