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TPS1H000-Q1: Apply samples - TI /TPS1H000AQDGNRQ1

Hao(SH) Zhang
Intellectual 865 points
Part Number: TPS1H000-Q1
Other Parts Discussed in Thread: TPS27S100

Hi everyone,

Here are a few questions about TPS1H000:

 

As you can see in below picture screenshot from datasheet. There is an internal clamping between Drain and Source to

protect this IC from a  reverse voltage by inductive loads.

When we powered the VS 23V and used a TVS to clamp the -1.1kV surge voltage to -40V, but the IC was broken.

1. My question is how much reverse voltage and how long can this internal clamping withstand?

 

We also do test: power the OUT  a -24V and power the VS 23V, which means the Vds is 48V，the IC work well.

2. Do you have any experience in this area or similar application scenarios? How many volts do you need to clamp the backpressure at?

 

3. According to the datasheet all the absolute maximum voltage are base on Device GND.

What is the maximum voltage between “CL” and “OUT”， “IN” and “OUT”?

 

Of course I welcome more notes and suggestions from you.

Thanks and waiting forward to your reply.

  • 0
    TI__Genius 16390 points

    Hi Hao,

    1. The more likely case for the device being killed is the max energy dissipation. If possible, it's best to ask customer to collect the voltage across VDS and current through the FET during the surge event, and see if the energy exceeds the maximum. Our industrial part (TPS27S100 for example) is rated to pass the IEC61000-4-5 surge tests.

    The other possibility is a -40V TVS will usually have higher clamping voltage (please refer to the TVS datasheet), and that might violate the max voltage rule. It's good to probe the output and see what's the actual voltage it got clamped to.

    2. We've seen various clamps. As long as the voltage and energy is within the spec, our device should survive. 

    3. There shouldn't be a spec for CL to OUT or IN to OUT as CL and IN are all refer to device GND and should be kept near 0V.

    The suggestion now is to check the voltage and the energy the FET has during the surge, and let me know once you hear back from the customer.

    Regards,

    Yichi

  • 0 in reply to Yichi Zhang.
    TI__Intellectual 865 points

    For Q1:

           channel 1: VDS       channel 2:  I_24V

    channel 1: Vout-GND      channel2:  I_ds

    These are the test picture. We added a TVS between Drain and Source the IC work well under the -1100V Surge. So please help me double confirm whether the IC energy exceeds the maximum, especially for the FET current.

    For :

    "The other possibility is a -40V TVS will usually have higher clamping voltage (please refer to the TVS datasheet), and that might violate the max voltage rule. It's good to probe the output and see what's the actual voltage it got clamped to."

    My customer think the 40V is the test value by differential voltage probe,  so I think it can be regarded as real value.

    Best, Hao

  • 0 in reply to Hao(SH) Zhang
    TI__Genius 16390 points

    Hi Hao,

    The second picture is too small to read. Could you get a clearer picture? Also could you ask customer to probe the VDS and Ids on the same scopeshot?

    One question:

    From the first picture, the max VDS is only 38V. From the original post, it says that "When we powered the VS 23V and used a TVS to clamp the -1.1kV surge voltage to -40V, but the IC was broken.". Did you mean 23V at VS and -40V at VOUT, which means 63V for VDS? Which one is the correct value? 38V or 63V?

    Thanks!

    Regards,

    Yichi

  • 0 in reply to Yichi Zhang.
    TI__Intellectual 865 points

    Hi everyone,

    The customer means 23V at VS and -40V at VOUT, which means 63V for VDS.

    And the next question:

    If use TVS to limit VDS to about 38V, what is the maximum current allowed to flow in 25us?

    We want to conform the max Ids value this IC can withstand in 25us.

    Best regards, Hao.

  • 0 in reply to Hao(SH) Zhang
    TI__Genius 16390 points

    Thanks Hao. I've followed up with email with the current spec. It would be good to ask customer to probe the voltage (Vin and VOUT) and also the current through the device at the same plot (the one requested in the previous post), and we can help further debug. Thank you!

    Regards,

    Yichi