Dear TI team, Kindly review the schematic and layout.TPS61022 Schematic docs & reference.rarTPS61022 Boost Gerber.rar
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Dear TI team, Kindly review the schematic and layout.TPS61022 Schematic docs & reference.rarTPS61022 Boost Gerber.rar
Hi prakash,
According to the layout, the output loop (VOUT-COUT-GND loop) is too larger, this could cause high SW voltage spike, which may damage the chip. And more, it's better to exchange the position of C7 and C2 to make C7 closer to chip.
I think it doesn't have to place R1 R5 R3 tooo close to chip, because those are steady voltage which do not change quickly. This may simplifier the layout.
You can also take this application note as reference.
Best Regards,
Nathan