TPS23881: With 0x7 Firmware version we are not receiving interrupt when PD is connected back in Semi Auto Mode

Hello Charan, 

Can you provide the contents of the interrupt mask register (0x01) and detect/class enable register (0x14) before and after PD connections? 

Regarding SRAM firmware version 0x3, it's still available in 2 places: 

1) slvc771a.zip as part of source code TPS23881Ref\Project\ccs\sram_code.c 

2) slvc772c.zip which is the installer for the TPS2388x GUI. After installation, the files TPS23881_SRAM.bits and TPS23881_PARITY.bits were available in this directory: C:\Program Files (x86)\Texas Instruments\TPS2388x\Apps\tps2388x\server\assets\devices\tps2388x. 

You can download both zip files from https://www.ti.com/product/TPS23881#software-development 

Regards,

Sai Gunda

Hi Sai,

Please find details of register values when PD is connected and disconnected 

1. Initially PD connected on channel-1 and it's up
---------------------------------------------------
0x1      : 0xee   
0x14    : 0x00
0x0c    : 0x24
0x10    : 0x11

2. PD disconnected from channel-1
----------------------------------------
0x1      : 0xee   
0x14    : 0x00
0x0c    : 0x00
0x10    : 0x00

3. PD connected back
-------------------------
0x1      : 0xee   
0x14    : 0x00
0x0c    : 0x00
0x10    : 0x00

We could download SRAM Firmware version 0x3, thanks for sharing the details. 

Regards,

Charan. 

Hello Charan, 

Register 0x14 should be configured to enable both detection and classification in semiauto mode. In other words, it should not read 0x00. It looks like you have completed at least one cycle of detection and classification, then a class 2 PD was detected, then channel 1 was powered on. This means that initially you did correctly configure 0x14 but the register was cleared for some reason.

Can you provide a register dump right before initially connecting the PD? 

Regards, 

Sai Gunda

Hi Sai,

Please find register details after connecting PD,

Initially before PD connection 0x14 is 0xff

when PD is connected we are enabling power in semi-auto mode.

Also, we are getting interrupts and those interrupts are cleared as well.

As part of interrupt clearance 0x14 also reset to 0x0

0x14 = 0xff

Once interrupt received,

We are reading interrupt register and all event registers

Configuring power on 0x19 register

Clearing interrupt using 0x1a

0x14  = 0x00

Regards,

Charan. 

Hi Charan, 

During this step: "Clearing interrupt using 0x1a" what value are you writing to this register? Before exiting the interrupt service routine, 0x14 should be set to 0xff to re-enable detection and classification of the PD.

Regards,

Sai Gunda

Hi Sai,

We are writing 0x80 on 0x1a. Which clears interrupt register, event registers and releases the INT pin.
we have implemented writing 0xff on 0x14 to re enable the detection and classification before releasing ISR and it is working fine now. 

Can you please confirm if it is the correct procedure to do and it's mentioned in datasheet that only for manual mode we have to write 0xff in 0x14. 

Regards,

Charan. 

Hi Charan, 

In manual mode, only one detection and classification cycle is performed when the corresponding bits in 0x14 are set. In semiauto mode, the cycles are continuously done until the channel is turned on. Register 0x14 is not automatically set in any mode. 

Regards,

Sai Gunda