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LM5069: Comparing the Tools for LM5069 and TPS2491

Komal Charan Garlapati
Prodigy 80 points
Part Number: LM5069
Other Parts Discussed in Thread: TPS2491

Hi, We are currently redesigning a Hot Swap Controller with LM5069-2. The old Hot Swap Controller was TPS2491. We are not changing the MOSFET. I was using the design tools of LM5069 and TPS2491 for comparing. 

I have few queries.

1. Even though we are using the same MOSFET, why is the recommended slew rate for TPS2491 and LM5069 different?

2. I have observed that in our design with TPS2491, we have exceeded the slew rate by a lot but the SOA margin is 1.5 which is good. I have observed that with increasing slew rate, the SOA margin is also increasing. How did the recommended max slew rate value is arrived, what happens if we exceed it?

3. For the LM5069 design, the recommended max slew rate is 4V/ms. When I keep the SS capacitor value as 4, the Start-up FET Power graph shows that at the starting, the power dissipation is around 28W. But if I keep the power limit as 17W, will it go into power limit mode and will it have any impact on soft start?

0447.TPS249x_8x_Design_Calculator_REV_B.xlsx1581.LM5069_Design_Calculator_REV_C.xlsx

I have attached the design files. 

  • 0
    TI__Guru** 105611 points

    Hi Komal,

    Thanks for reaching out!

    Please find my comments below

    1A) The GATE sourcing currents are different so the recommended slew rates will be different.

    2A) Please unlock the tool with password LM5069 or TPS2491 to view the background calculations on the recommended max slew rate value. Let me know if you still have questions.

    3A) yes, it triggers power limit fault and comes out of it as soon as power dissipation falls below 17W. It is recommended to set slower slew-rate in dvdt mode.

    Best regards,

    Rakesh

  • 0 in reply to Rakesh
    Prodigy 80 points

    Thank you Rakesh. 

    Also, I wanted to know what happens if we exceed the recommended max Slew Rate. Could you please let me know?

  • 0 in reply to Komal Charan Garlapati
    TI__Guru** 105611 points

    Hi Komal,

    As you increase the slew-rate, the start-up will be faster (shorter startup time) which increases the transient power dissipation in the FET for a given startup load. This significantly reduces the SOA margin during startup for the design.

    Best regards,

    Rakesh