My customer have two questions for the SS behavior in our EVM. As in following pic, Why the Vout not start up during the T1? Why the SS ramp up so quickly during the T2?
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
I verified that this is the correct behavior. I do not know the mechanism for T1 but I can see if I can find out. T2 begins after 1.7 x ss time. After that time, the SS pin is pulled up to the internal VREG5 voltage.
From the IC designer:
"I add the one Vbe voltage shift function of the SS pin for the latest CS version.