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TPS61040: Absolute Max for SW Node

Part Number: TPS61040

Table 6.1 "Absolute Maximum Ratings" in the Datasheet lists 30V as "Absolute" MAX and MIN of the SW node.
I assume there is some minimum voltage limit for the device (i.e. -0.3V); can you confirm this value please?
Is there another parameter like "-3V for <10ns is also acceptable" or something? Some devices have this rating for SW as well...

Regards,
Darren

  • Hi Darren,

    The expert supporting this part is on holiday leave. He will reply you after next week. Thanks.

  • Hi Darren,

     Sorry there is a little mistake of this Datasheet, the MIN voltage of SW node should be -0.3V, not 30V.

     And also we don't have the SW spike voltage parameter, this device is an old device, we can't find this parameter now.

    Best Regards,

    Nathan  

  • Hi Nathan,

    I understand we don't have SW spike voltage data available anymore.
    Still, is there any comment we can provide on the attached waveform?
    (i.e. "this level of negative transient should be acceptable", etc)
    This is the SW node and the ripple has moments where spikes reach ~-3V for sub-[ns] time lengths.

    If we can't provide a comment like above, can I get your thoughts on the below?

    The SW pin just connects to a N-FET and the ABSMAX ratings relate to this FET.
    The max-30V is the maximum Vds of the FET, while the -0.3V comes from the intrinsic diode of this FET; and going beyond this range causes shoot-through currents (current flows from GND to SW node) that could damage the FET.

    Is that statement accurate? 
    Given your(or the teams) experience with DC/DC devices, do you have an opinion (no guarantees) on this?
    Does it seem like -3V for <1^2[ns] might be acceptable, but that we can't guarantee it? Or from your experience is this a big no-no?


    堀内_SW波形_TPS61040DBVR.pdf

  • Hi Darren,

    The max-30V is the maximum Vds of the FET, while the -0.3V comes from the intrinsic diode of this FET; and going beyond this range causes shoot-through currents (current flows from GND to SW node) that could damage the FET.

    Correct, and one more reason is that the negative voltage limit is related to some parasitic structures inside the chip, this may also cause abnormal behavior  or even damage.

     About the waveforms, I want to make sure that if the measurement technique is correct, because improper measurement method will cause larger voltage spike than it actually is. You can take this article as reference (page 3~5).

    And more, I think it would be better if customer can provide their layout, so that we can check if there is any voltage spike risk caused by bad layout. Thanks.

    Best Regards,

    Nathan