Hello team,
The customer has a question how to connect between LMZ31710 RT/CLK pin and FPGA IO for external clock as below.
They would like to use RT mode at power up, then change external clock mode.
FPGA IO has a weak pull up resister (several tens of kohms) , so they are concerned that the pull up resister effect switching frequency at RT mode at power up.
So they would like to know how to connect. Would you please advise?
Best Regards,
Akihisa Tamazaki
Hi Akihisa,
An AC coupling circuit is recommended to interface with the LMZ31710. This is needed so the frequency will be correctly set with the RT/CLK resistor if the clock source is unavailable.
Technically we could connect the clock source directly to the LMZ31710 RT/CLK pin but generally this is not recommended. The direct connection is only allowed if either the clock source is high impedance when not available OR the application can ensure that the clock source is always available for the LMZ31710 when it is enabled.
If the LMZ31710 is enabled and the clock source pulls the RT/CLK pin high or low, the switching frequency will be unpredictable. If the clock source goes low it pulls a lot of current of the RT/CLK pin so the fsw will be very high. If the clock source goes high there will be no current out of the RT/CLK pin so the fsw will be really low.
In the discrete AC coupling circuit below, we suggest including a series resistor to the AC coupling capacitor and a schottky clamping diode like what is on the TPSM84824EVM. The schottky diode clamps the negative voltage and the series resistor limits the current through the diode to keep the Vfwd voltage low. Image below.
Let me know if you have any additional questions.
Yitzhak
