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Original question:

UCC28782EVM-030: UCC28782 UNDER WT6636 CONTROL

UCC28782EVM-030: UCC28782 XMFR POWER LOSS

robin gangopadhya18
Mastermind 6296 points
Part Number: UCC28782EVM-030
Other Parts Discussed in Thread: UCC28782, , ATL432

Hello:

We have some UCC28782 based modules: assembled with values close to the UCC28782EVM-030 EVAL KIT. Right now, input is rectified AC with sufficient input filter and hold-up capacitor values.

Output is 20V. Our intention is to load it up with 5amp cc. Rcs=.075 Ohms, Eventually, for an USB C PD/charger at  100W

Wired xmfr temperature goes to 125 deg, does not seem like attaining steady state even then. However, the wires do not seem to be anywhere near this temperature. Meaning, skin loss, proximity loss, DCR loss are acceptable. 

Xmfr parameters are quite good: Lpri=80uH, gap=1mm approx, Lkg approx 1.5uH, Cww approx 80pF. Cross section= 108mm sq, Npri=25, Naux=5, Nsec=5

Estimated Bac is approx .14T from switching freq around 176 kHz. From input conditions: Line 160V, pk rectified voltage= sqrt2*Vline. Duty approx 30%.

Clearly, there is something wrong!

From some TI publications ( Keough & Cohen etc ), it seems we are ignoring adverse effects due to DC bias ( referred to a Ph.D. thesis from VT)..  

We are following the SLUUC646C spreadsheet. I suspect that only can provide ac flux estimations from V, Ton, Npri. Does not include DC bias on the core. Specifically how it will shift up Bac-peak.

Then we have to estimate Hdc=NI/Lmag. That is not significant given the gap. So only asymmetry is B excursion creates a "bias" trend.

Then by lowering the Bac , would you not lower Bac+Bdc?

Is that a good direction to go?

We are going to try Npr=40, Ns=Naux=8, keeping the same ratio. But there is a penatly : we have a multi-layer planar xmfr for production case, and it will be hard to accommodate so many turns.

Any review of this high temp in the core will be highly appreciated.

r

  • 0
    TI__Genius 16155 points

    Hi
    I have assigned this thread to product expert. He should be able to respond within 2 business days.

    Regards

    Manikanta P

  • 0 in reply to Manikanta Pallantla
    TI__Mastermind 40580 points

    Hello Robin, 

    There may be some theoretical effect on core loss with a DC bias (same for all flybacks, for instance), but I don't think that effect will result in a hugely  significant temp rise. 

    I suspect that your transformer may be heated internally by copper losses due to fringing fields from the 1mm gap.  Any windings within 1~2mm of this gap are subject to eddy currents from the fringing field arcing out away from the gap.  The temperature of the wires near the bobbin pins may not reflect the heating going on at the middle of the bobbin.  

    What is the core size and material, please?  Perhaps a different size, shape, and AL value can lend itself to reducing the width og the gap needed for your application. 

    Regards,
    Ulrich  

  • 0 in reply to Ulrich Goerke
    TI__Mastermind 40580 points

    Hi Robin, 

    As mentions in my reply to your parallel post, I am copying your text over to here and have closed that thread. 

    "Hello

    We made a xmfr 40:8:8

    Which should have reduced Bac 60%, thus hopefully, DC bias value.

    But it did nothing to reduce core temp. We ran 100W ...stopped when inside the core temp went up to 130 deg C.

    Temp rise is not due to B it would seem.Not due to Hdc either.

    In this case. the quick turn-around xmfr in our lab got 1.6 times DCR!

    This might explain why temp stayed the same IF NOT HIGHER.

    Should we redo with the same DCR as in the 25:5:5 case?

    Then only we can tell if proximity or eddy losses are major players. This latter will mean the core material is not power ...But it is EPCOS N87 I think...

    Any comment will be highly appreciated.

    r" 

    Part of my reply was "As your resistance measurement suggests, I think the heating comes from eddy-current losses due to wide fringing fields from the gap. "

    Also please let me know what kind of wire you are using for the windings.  At 176kHz, both primary and secondary windings should be using Litz wire with base strands of at least 38AWG, maybe even 40AWG or 42AWG.  (I'll have to check my wire catalog for freq vs. Litz sizing, to be sure.)

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Mastermind 6296 points

    Hello Ulrich:

    Sorry for the delay: had some medical issues.... but we followed up with your insights...first, let us get the xmfr details  given herein:

    Turns ratio: 1: 0.2: 0.2( 25T:5:5T)

    - Core set: EQ30

    -Material: N87 EPCOS

    - estimated switching freq observed: 176 kHz. This gives a skin depth of about 0.150 mm for copper wire.

    Case A: 5 Amp, 20V output, input-  Vrectified;approx 225V

    _Pri wires:  25 T, 2 strands of 33AWG x 2 layers ( as suggested in the paper by Keough & Wang in ADJ 4Q 2020.

     33 AWG dia= .18mm

    So 4 strands total. DRC approx  0.45 ohm

    -Sec: 4 strands of AWG 32 x2 layers. DCR= .06 Ohm

    -Gap: on each leg of  1 core half: 12mils. So  gap is "distributed" not a big gapping space of 28.8 mils in the center post of the  xmfr! Calculated value of Lg is .75mm or 30mils.

    The temperature-(inside the bobbin)  in this case goes to 135 deg C & slowly creeps up. Took 1 hr.

    Case B: 3.5 Amp, 20V output, Vrectified;approx 225V

    The temperature-(inside the bobbin)  in this case goes to 110 deg C & slowly creeps up. Took 1 hr.

     

    Case C:  Core ETD 34/17/11, Ae=97mm^2

    Turns ratio: 1: 0.2: 0.2( 25T:5:5T)

    -Material: PC40 TDK

    5 Amp, 20V output, Vrectified;approx 225V

    _Pri wires:  25 T, 1strand of 24AWG x 2 layers ( as suggested in the paper by Keough & Wang in ADJ 4Q 2020. 24 AWG dia= .5mm

    So 2 strands total. DRC approx  0.09 ohm

    -Sec: 4 strands of AWG 24 x2 layers.

    So 8 strands of 24 AWG, DCR= .002 Ohm

    -Gap: on each leg of  1 core half: 12mils. So gap is "distributed" not a big gapping space of 28.8 mils in the center post of the  xmfr!

    WINDING FOLLOWS PRETTY CLOSE  TO STAN ZUREK'S PAPERS "Qualitative  FEM ANALYSIS  OF PROXIMITY EFFECT LOSS REDUCTION"

    He found minimizing layers is the key- optimum being 1P-1s-1P, each Pri is fully wound on a long coilform  hence the core ETD34/17

    The temperature-(inside the bobbin)  in this case goes to 110 deg C & slowly creeps up. Took 1 hr.

    If we run this core with CC load of 3.5 Amp, temp will stay around 90 deg C

    We did not find MUCH significant reduction in temperature rise.

    In reality, DC bias in our case is also not significant. 

    This needs "qualification" because what does the DC bias alone on a coil do? There is no dB/dt to cause induction. They should qualify it by saying DC bias shifts dBac upwards- thus making Bmax higher than calculated only as dB from Faraday's laws. 

    So our xmfr with 40T-8t-8-t would have made a difference. BUT IT DID NOT, with other parameters almost remaining the same.

    BUT THERE HAS TO BE A WAY TO KEEP CORE TEMPS AROUND 70 DEG( RISE OF 30 DEG ABOVE AMBIENT).

    I am suspecting dB/dt might play a role; given we use GaN in the primary switches. NV6117 both.

    Or is the attached paper from  Boyorovic group a way out? Our style of gapping is almost what they suggest- parallel to the coil & orthogonal.  But , even that I suspect gives rise to any spectacular temp reduction.

    If this “USB D” PD or charger is to be portable, then we cannot have inside a furnace-type activity going on at 135-140 deg C!

    Eagerly waiting for your comments.

    AC_LOSS_REDUCTION_BOROYVIC.pdf

  • 0 in reply to robin gangopadhya18
    TI__Mastermind 40580 points

    Hello Robin, 

    I apologize for my delayed reply. 

    There are a lot of cases and variations here to sift through, but after significant effort, I think three is a misunderstanding about the winding structure in the Keogh and Wang paper in ADJ 2020 for case A.  If so, this misunderstanding appears to have propagated to the other cases as well. 

    For case A, you mention that there are 25 primary turns "2 strands of 33AWG x 2 layers" and "...4 strands total."  I interpret this to mean that you have 25 bifilar turns for an inner primary and another 25 bifilar turns for a parallel-connected outer primary winding.  Figure 3(a) in the Keogh and Wang paper show the primary winding is split in series, and 1/2 wound for inner layer and the 2nd 1/2 wound for outer layer.  This is the normal structure for split-primary windings "sandwiching" a secondary winding.  A series connection guarantees that both 1/2-windings carry the same net current. 

    A parallel-wound primary cannot guarantee that the inner current and the outer current are equal, hence the R losses cannot be determined by the resistance of "4 strands total" per turn.  At the extreme, all primary current may flow in only the outer winding, so you could have twice the current in twice the resistance (neglecting all the AC effects and length per turn differences) for 8 times the copper loss that you expected.  The reality is probably somewhere between prefect sharing and zero sharing, but who knows how far to either end? 

    If my interpretation is correct, I suggest to re-wind Case A such that you have 13 turns of 4-filar 33AWG (or 34AWG, if 4x33AWG x 13T won't fit) for the inner winding and 12turns of 4-filar for the outer primary for a total of 25 turns.  

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Mastermind 6296 points

    Hello Ulrich:

    Agreed!

    But right now, we have a different nightmare to handle. Seems, the "electronic load" is causing all sorts of problems(bought cheaply from the A world, after our expensive HP went caput..no one else would have shipped in 1 day another...)

    All 4 modules are dead- sudden death syndrome- perhaps causing leaky NV6117- WE ARE LOOKING INTO IT  due to unknown turn-on/turn-off load behavior- all i in SR, including a hefty 400V diode when we ran out of EPC2034...and 150V MOSFETs...

    All NOW GIVE 1.5ms drain switching, output hardly rising, when it shuts down. A while ago, we had them running at 100W...

    (it is not in the xmfr damage).

    1. mind-boggling situation out of the blue...let us sort these out first before we fix xmfr loss(may be caused by the faulty load?)

    will report asap. thnx for your time

    r

  • 0 in reply to robin gangopadhya18
    TI__Mastermind 40580 points

    Hello Robin, 

    I'm sorry to hear about these side issues that are interfering with your system development. 
    We are ready to help further, as soon as you are able to resume.

    In the meantime, I will close this thread.  You can reopen it later or start a new one when you're ready.

    Regards,
    Ulrich 

  • 0 in reply to Ulrich Goerke
    Mastermind 6296 points

    Hello Ulrich:

    Here is what we found. The ATL432 was busted: we located it after a whole series of troubleshooting steps.

    How will it ever be possible for the shunt regulator to go bad other than a transient from the Load box during a power-off time?

    ATL432  buried deep & surrounded by high-value resistors excepting the power return line( & +20V output).

    We are abandoning this A box, for now, ordered another from the company whose digital scope we are using successfully.

    Meanwhile: smile!..in a xmfr which is a trial run with 5 paralleled strands in 5 layers - the difference in currents among 5 strands of secondary is a whopping 47%.

    Not acceptable.

    So got to change that before we proceed to go to 5amp.

    fyi

    More will be reported...

  • 0 in reply to robin gangopadhya18
    TI__Mastermind 40580 points

    Hello Robin, 

    Thank you for your debugging update.  
    I wish you well with your transformer redesign and look forward to further good news. 

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Mastermind 6296 points

    Hello Ulrich:

    It took us a long route to get the correct xmfr..load...testing some key things etc.

    But , at 68W, we did get the inner temp to 64 deg C- a very nice situation indeed.

    This xmfr winding was DIY litz. So we thought we would do a  "better" finish etc.

    It turned out that it had 6uH lkg. 70pF Cww, Lri~95uH

    I thought of trying it out.

    Lo & behold, it struggled to work, with some typical spattering audio...we stopped it & thought of vac impregnation.

    But then it did not work at all.

    To boot, the  Depletion mode TVS diode. died- taking with it the controller....must have occurred while it was struggling to  start up.

    Now, I need to stop here. The question is: why the TVS ? & then the controller- because of leakage ?

    Any background on this?

    Appreciate as always your enlightening comments.

    -r

  • 0 in reply to Ulrich Goerke
    Mastermind 6296 points

    Hello Ulrich:

    I missed out another big failure: we now have a BSC110N150 D2PAK  SR, for now we do not use EPC2034 due to difficulty in maula assembly.

    THAT  had failed with the xmfr with 6.4uH leakage.

    I have noticed that any MOSFET with rev recovery under certain abnormal modes of operation, fails. 

    I suspect that is due to the excessive dissipation during the neg- positive transition at the drain of the SR.

    I thought it is important to add this failure report here in the context.

    r

  • 0 in reply to robin gangopadhya18
    TI__Mastermind 40580 points

    Hello Robin, 

    It is difficult to determine what could have caused those failures, though it is possible that one failure led to cascading follow-on failures if the energy in that first failure was high.  Failures result from some overstress on one of the components, such as too high spike voltage, too high current, too high temperature. 

    Changes in the system circuits may have changed the amount of stress that one of the parts was previously sustaining. 

    With the redesigned transformer, the leakage inductance increased. The ACF topology seeks to resonate the leakage energy to the output using the clamp capacitor and the secondary-side resonant capacitance.  With a change of Llk, the resonant frequency changes, so if Cclamp and Cres were not also adjusted to keep the resonance within the previous demag time then its possible that all of the excess energy could not be transferred and the remnant was great enough to break over a transistor.  Possibly starting a chain reaction. 

    Changing the output rectifier from eGaN to Si also increases the switched node capacitance.  All circuit changes need to be assessed as to there impact on the ACF topology.  Basically, if you change one thing, you will often have to change a few other things to accommodate the effects of first change. 

    I don't know why the depl-Fet and its TVS died... but each will have seen an overstress beyond what it was capable of sustaining.  With so many parts failed, it is difficult to conjecture what failed first and set up overstresses for the rest of them. 

    I recommend to use the Excel tool to recalculate all the parameters based on the new components being used. 

    Regards,
    Ulrich  

  • 0 in reply to Ulrich Goerke
    Mastermind 6296 points

    Hello ULrich:

    got it: thnx.

    We are looking for each item you mention.

    Most of the time, we can pretty quickly locate where failures occurred - mostly from hook-up errors these days.

    But, it gets impossible on a board that was supposed to be your work-horse.

    we will find it- a matter of time & nerves!

    thnx much

    -r