LM5032: Maximum Duty Cycle

Hello,

From the parameters used in your design, the max duty is estimated at 41.8%. I am not sure what is exact reason to get 51.5%. Maybe 40.3k is too big? but the datasheet doesn't have max limits. As you said, 36k works fine. Can you try low UVLO? Lower UVLO from 1.4V to 1.3V, then 36k may give higher max duty as you want. 

By the way, do you test the device on your board or TI EVM? 

I tested the part on our PCB not a TI EVM. Please note, we already use the part in another design where the duty cycle is not so critical, and this is already established in production in volume, so we have experience of using this part.

The variation of duty cycle, as you stated correctly is not specified on the datasheet, but TI provided statistical data in another thread.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/881645/lm5032-maximum-duty-cycle-error

The 50% maximum duty cycle is critical since core reset must happen in the forward converter design.

I have a 12V supply and a resistor divider of 75k and 10k, giving 1.4V on the UVLO pin.

The requirements of my design requires me to push the duty cycle to the maximum, and this is why I need to understand why I am not seeing the duty cycle as per calculated with 40.k resistor for DCL & 68k RT.   The voltage on the UVLO pin will only drive the duty cycle lower, but this is NOT what we are seeing. For an UVLO pin of 1.4V, and above resistors I see 51.5%.  Even with worse case numbers from the distribution chart, this shouldn't happen, it should be much less. 

I have tested many parts both with the feedback connected, and also setup as per datasheet with feedback open, always 51.5%.

Thanks.

The typical max duty is 76% from the below table. Test conditions: RT = RDCL = 42.2k,  UVLO = 1.3V, VCC =10V. Can you measure the real duty? If you use this duty as starting point, what duty cycle do you get? Then you may reduce RDCL to smaller value, and calculate the max duty and compare what you measure. I doubt  a different RT from the below table may create some variation. 

Thanks Sean for your input. I have arranged for resource for more testing as per your suggestion and will update as soon as.

Thanks.

Further testing has now been carried out, as suggested by TI, with RT and RDCL both set to 42.2k.  UVLO pin was measured to be 1.17V (<1.25V) with Vin supply = 10V, with IC off condition. Increasing supply to 11V resulted in IC running. Vin gradually decreased to bring UVLO pin voltage to 1.25V as per suggestion. This was achieved  when Vin was 9.5V. At this point, the max duty cycle observed was 75.7% on OUT2. In line with datasheet of 76%.

Also observed, a discrepancy between duty cycle time of OUT1 and OUT2. In this case, OUT1 was always 1.5% less than OUT2. This has been observed on many parts.

Going back to the original issue, which is with 68k as the RT resistor (the value I require in our design), and with RT as 40.3k. This yielded a max duty cycle of 50.3% on OUT2, which is in disagreement with the 47.4% calculated using equation in datasheet. This assumes worse case point, given in bell distribution curve 82%. The curve is linked previously in this thread, given by TI.

Since I require to push the duty cycle as far as I can, I need to know the correct spread to ensure products do not fail.

Thanks.

I told to my colleague about the issue. He wonder if you can share your schematic to help analysis.

Thanks.

Thanks. We will review it.

At open loop, the out1 and out2 are generated individually by internal comparator , diodes, resistors.  It is common to have some difference between them. but at the closed loop, the difference can be corrected,

About max duty, it need more efforts to understand. 

I understand RT has to be 68K. UVLO has to be 1.4V for your design. Please correct me if I am wrong. Assuming I am right, use the below steps:

1). RT= 68K, V_UVLO =1.4V, RDCT =68K.    Measure the duty OUT1 and OUT2;

2). RT= 68K, V_UVLO =1.4V, RDCT =40.3K.    Measure the duty OUT1 and OUT2;

This can tell us full information about max duty and how RDCT to affect max duty.

I will upload a response tomorrow.

asd

For maximum duty cycle, TI give an additional formula on their forum, which is Max_Duty-(UVLO-UVLO_Min)*21.54,  where Dmax is 80% at UVLO_min value of 1.25V. The duty cycle then changes by 21.54% for every 1V change in UVLO voltage.

This formula can be seen in the graph below as plotted on the GREEN line. However, a more accurate formula can be derived from the standard straight line equation y=mx+c and by referring to the datasheet tabulated data, again shown below.

In this case, m  = (80-20) / (3.75-1.25)      m =24.    c can be determined as 110 from a specific point  80 = 24 x 1.25 + C.

Dmax is then given by 110-24*UVLO, and this is shown with the RED line.

For our application, it has been shown that by setting UVLO to 2.7V nominal value, with Rt and Rdcl set as a ratio of 1, eg both resistors 68k, the error is smallest, with the duty cycle accurately set by UVLO voltage.

The UVLO has a current source of 20uA, and tolerance of 16uA to 24uA, while previous TI forum shows a spread on the duty cycle of +/-8% as shown below. Does the 8% error include the tolerance on the UVLO or not. I suspect not, because the error due to UVLO current source can be controlled by making the voltage divider at that pin stiff (higher bias current) relative to the 20uA source.