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UCC5870-Q1: clarification on adjusting GD strength on the fly and CRC check

Part Number: UCC5870-Q1

Hi

We know that the drive-strength can be altered in steps of 1/6 (so, 1/6, 2/6, 3/6, 4/6, 5/6 & 6/6) by appropriate binary values programmed into CFG8 register bits 0 to 2.  The datasheet states that this “on the fly” feature requires CFG8 bit 6 (=CRC_DIS) set to 1.  Does it mean if we were to utilize the drive-strength feature then CRC-check feature is not at all available during the whole of that Active session?  We understand that, provided CFG8 bit6 is set to 1, CFG8 bits 0 to 2 can be repeatedly re-programmed in that whole of Active session.

Thanks

  • Hello Aivaras,

    If the CRC check is enabled when the gate drive select bits are changed a fault will be reported. This is because the CRC includes the drive select bits, so if they change the crc fails. So you are correct, if you need to change the drive strength during the active mode the CRC check will need to be disabled and won't be available for the entire session.

    As another comment on the adjustable drive strength, please be aware that external factors such as the gate resistance can dominate the output current, meaning that the actual drive strength in a system may not change much when the drive strength bits are changed.

    Please let me know if this answers your question by clicking the green button, or let us know how we can continue to help.

    Regards,

    Daniel

  • Hi,

    Thank you and some feedback.

    Since the CRC check for the integrity of the drive-strength bits is moderately critical, perhaps TI should consider upgrading the design by providing the option of excluding just these drive-strength setting bits from CRC-check. Will this be addressed in the new generation?

    Thanks

  • Hello Aivaras,

    Thanks for your feedback!

    We are taking this into account as we work to design our next programmable gate driver.

    Regards,

    Daniel