TPS7A26: ESR, Stability, and the LDO Regulator

Hi Sveinn,

Newer LDO architecture control loops are designed such that the lower ESR of COUT will not shift the zero of the function enough to allow the phase margin to become unstable. The control loops have internal poles and zeros set to control the stability and allow for much lower ESR capacitors that were not yet popular on older designs. Nowadays ceramics are the most ubiquitous capacitor and they have very low ESR, so the newest devices are being designed in to be stable with very minimal to no ESR on the COUT passive.

That is to say: Earlier larger sized capacitors with high ESR were the industry standard and therefore the design of LDO's utilized the lower frequency Zero from the output capacitors in order to stabilize the loop. Newer ceramic style capacitors push the zero to too high of a frequency to be able to stabilize the loop so the design now has to have internal stabilization, which is their own zeroes, this allows the new architectures to be stable even down to 0Ohm ESR on COUT.

The two turning points are due to the output capacitor. This section is beyond the bandwidth of the LDO and is dominated by parasitics and COUT. The downslope up to ~200k is the LDO bandwidth, which is dominating the response curve of the plot, but at around that frequency the capacitive portion of COUT's impedance curve begins to become dominant. This causes the PSRR to improve until the point at which the resonant frequency of the capacitor is reached. This is the second peak that you have circled in the diagram. After this region the COUT's impedance becomes dominated by the inductance of the capacitor which once gain causes a downturn due to the zero. 

Regards,

John