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UCC28951-Q1: Understanding ADELEF and transformer shortcircuiting

Gokhan G.
Intellectual 775 points

Part Number: UCC28951-Q1
Other Parts Discussed in Thread: UCC28951

Hi,

I'm investigating TIDM-020031 and working on UCC28951-Q1.

Please, refer to schematics based on TIDM-020031. It is a PSFB CDR. Transformer secondary winding has only one winding and SR.

Considering CCM operation

1) The IC has ADELEF pins. It sets delay time between OUTA or OUTB turn-off and OUT-E and OUT-F turn-off. Why does user need this dead band? Which achievements are made in the topology by using this dead band?

2) How does IC achieve ZVS on synchronous rectifier mosfets? Is it achieved by short-circuiting primary and secondary windings of transformer at the same time?

3) There is an interval that both primary and secondary windings of transformer short-circuited by MOSFETS. What is the purpose of doing this? Does the topology use that stored current in transformer to charge coss of MOSFETS?

4) Could you please provide any other documents to understand the operation of using ADELEF ?

Thank you in advance.

  • 0
    TI__Guru* 86286 points

    Hello,

    1.  You are correct the that the ADELEF pin is used to delay the turn-off FET QF in regards to QA turnoff, and the delay turn-off of FET QE in regards to QB turnoff.  This is shown in figure 31 of the data sheet.  The idea behind this was to reduce body diode conduction of FETs QE and QF by adjusting the ADELF timing.

    2.  The phase shifted full bridge only has ZVS on the primary FETs and not the secondary rectifiers.

    3.  You are correct that the SR FETs on the secondary can be on at the same time during the free wheeling period.  At the time the systems engineer that defined this device thought that this would help reduce conduction losses on the secondary.  However, it did up reducing body diode conduction on the secondary when the SRs came out of free wheeling.  This drove the efficiency up roughly 0.5% in a 600 W design.  So the systems engineer decided to leave this feature in the controller.

    4. When it comes to ADELEF TAFSET and TBESET should be set to 1/2 the turron delay between A and B, C and D.  This ensures the SRs are on when energy is being delivered from the primary to secondary of the phase shifted full bridge.  The following link will bring you to an application note that describes how to design the UCC28951 in a phase shifted full bridge.  In section 13 the application note reviews how to setup the timing for the turn-on delays of FETS A, B, C, D, E and F.  Equations 138 through 144 go into detail on how to setup the timing for ADELEF and DELEF.

    https://www.ti.com/lit/an/slua560d/slua560d.pdf

    Regards,