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TPS1H100-Q1: Questions about VDS clamp

wang wan
Prodigy 150 points
Part Number: TPS1H100-Q1

Hi

   From datasheet, we can see that information below: VDS_clamp=VBAT-VOUT

We think the clamp should be between Drain and Source. However, it shows it is between Drain and Gate. Is there anything wrong? Why will the clamp between D and G protect FET?

  • 0
    TI__Genius 16390 points

    Hi Wang,

    The clamp is between VGD. During OFF state, the gate voltage is pulled to the Source voltage. When the Drain voltage keeps rising, the VGS clamp will engage, and gate voltage will be pulled up (away from the source) to the VBAT-VCLMAP. Once VGS exceeds the Vth, the MOSFET is turned ON to clamp the Source voltage by the VGD clamp voltage.

    Regards,

    Yichi