LP876242-Q1: Enable EN_RDV at GPIO1 pin

Hi BU team

what's the updates?

Thanks 

Hi Ted,

For the CRC calculation each byte is given to the CRC calculation function separately and previous CRC result is used for the next calculation.

/*
 * Calculate the transmit CRC
 */
crc = 0xFF;
crc = crcCalc(addressByte, crc);
crc = crcCalc(pageCtrlByte, crc);
crc = crcCalc(g_data_buff[ii], crc);

Here is the crcCalc function used.

uint8_t crcCalc(uint8_t data, uint8_t crc)
{
    uint8_t newCrc, scratchByte, currByte;
    volatile uint8_t ii;

    newCrc = crc;
    scratchByte = data;
    for(ii=0;ii<8;ii++)
    {
        currByte = (scratchByte & 0x80) ^ (newCrc & 0x80); // XOR MSBs
        newCrc= newCrc << 1;  // rotate crc left by 1
        if(currByte)  // result of XOR MSBs was one
        {
            newCrc ^= 0x06;  // XOR bits which were previously in locations 0 and 1
            newCrc |= 0x01;  // Bit 1 position is the result of the XOR MSBs
        }
        scratchByte = scratchByte << 1;  // rotate data by 1
    }

    return newCrc;
}

BR,

Samuli

Hi Samuli

what's the comments on the first question? Add some information for reference. 

1. My customer Freetech used LP876242 to provide the power supply to AWR2243+TPR12. In customer application, GPIO1 need to be re-configured to EN_DRV function. After the system is powered up,  write 0xA1=0x98 and 0x31=0x21 then GPIO1 pins (acted as EN_DRV function) became low level from high level (acted as GP0 function) while the output rails kept unchanged.

And the readback of INT registers are listed below.

0x5A         0x0A

0x5B         0x00

0x5C         0x00

0x5D         0x00

0x62         0x40

0x63         0x00

0x64         0x00

0x65         0x02

0x66         0x00

0x67         0x00

0x68         0x00

0x69         0x00

0x6A         0x00

0x6B         0x00

0x6C         0x00

Only VMON2_UV_int was detected. Based on datasheet, the VMON2_UV_INT doesn't pull EN_DRV low. 

Would you help share your comments on this issue? what's your suggestion if customer want to re-configure GPIO1 pin as EN_DRV function in their application?

The samples are with Rev1 NVM.

Thanks 

Hi Ted,

GPIO1_CONF would need to be set to 0x2D in order to properly configure it as EN_DRV. Currently GPIO1 is configured as an input with the 0x30=0x20 write.

Also are you using LP876242B0RQKRQ1?

Thanks,

Daniel W

Hi Daniel

Yes, LP876242B0RQKRQ1 is used by my customer and it is only available OPN to customer at this moment.

In the NVM setting file<LP876242B0RQKRQ1_rev1_NVM_config_validation_25Feb22> shared by BU team, GPIO1 is configured as GPO with internal PU to VCCA where 0x31=0x1

Are there new changes on GPIO1 configuration in latest NVM setting? 

Thanks 

Hi Daniel

Customer tried sending writes 0xA1=0x89 and 0x31=0x2D but GPIO1 pin still output low level after writing. 

what's your comments? and can LP876242 GPIO1 support to be re-configured EN_DRV after system is powered up?

The force_en_drv_low bit and enable_drv bit are not write by SPI. 

Thanks 

Hi Samuli, Daniel

So it is not supported by LP876242B0RQKRQ1 that GPIO1 is re-configured as EN_DRV function via SPI interface after the system is powered up. Right?

if this request from customer is met, need a new OPN with different NVM setting. Is it true?

Thanks