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TPS7B4254-Q1: Shortcut to battery performance & protection

Fausto Garcia
Prodigy 90 points
Part Number: TPS7B4254-Q1

Hello,

  I am simulating with tracker TPS7B4254-Q1, and I have some questions, but first of all, let me clarify about you can see in the schematic in PSPICE:

    

-  I had to place high impedance resistors at NC and PAD pins to avoid errors.

-  I am simulating a shortcut to battery (32V) .

-  Input to tracker is an internal power source of 5.5V.

-  ESR is there to decrease high voltage oscillations at pin 5 (Vout), in principle this could be an option, but other impacts would need to be analyzed.

 And these are the results:

                  

    My questions are:

1.- According to specs, maximum operating voltage at VOUT is 40V, so, I am assuming that in this particular situation (shortcut to battery - SCB) , device is able to survive to this voltage peak, is this right?, actually this condition is also met:

      

2.- Looking at the input current in VOUT pin during this SCB, you can see a peak about 5A - entering to the device -, I do not find specifications in this regards, is the device able to withstand this current peak?

3.- Is the output settling time shown something expected, around 1.4ms ?

     

4.- is this protection method compatible with the device:  ?

     

Thank you.

  • 0
    TI__Expert 6450 points

    Hey Fausto,

    1. The device should survive the Vout from the battery and the difference between Vin and Vout in this case since you are within the absolute max ratings.

    2. This device has an internal back-to-back PMOS to aid in these scenarios where there is a short circuit to a battery. There is no specification regarding the limit of this reverse current, however as long as the back-to-back PMOS can withstand it then the LDO should remain protected.

    3. How quickly does Vin and Vadj take to reach your desired value?

    4. As mentioned previously, this LDO has back-to-back PMOS to help in the case of a short to a battery. However, using a reverse current protection diode still helps with this problem.

    Regards,

    Andres

  • 0 in reply to Andres Sagredo
    Prodigy 90 points

    Hello Andres

    In regards to question 3,  I have been checking also this other device :

    TPS7B4253-Q1

    and it does not show this kind of delay of 1.4ms --  Vout to reach Vadj value--

  • 0 in reply to Fausto Garcia
    TI__Expert 6450 points

    Hey Fausto,

    The delay for TPS7B4254-Q1 should definitely be much shorter than that according to this forum answer and the other device you have measured.

    I am worried it might be the model for TPS7B4254-Q1 that may be giving you issues. Would it be possible that you share the models for both LDOs to compare? 

    Also, did you get both models from TI's website?

    Regards,

    Andres

  • 0 in reply to Andres Sagredo
    Prodigy 90 points

    Hello Andres

    Here you are, both from TI website

    slvmc85.zipslvmc86.zip

    tks

  • 0 in reply to Fausto Garcia
    TI__Genius 12511 points

    Hi Fausto,

    Andres will get back to you as soon as he can, thank you for your patience

  • 0 in reply to Fausto Garcia
    TI__Expert 6450 points

    Hi Fausto,

    Thank you for providing this information, I'm going to analyze the model. Allow me 2 to 3 business days to get you more information.

    Regards,

    Andres

  • 0 in reply to Andres Sagredo
    Prodigy 90 points

    Hi Andres,

    Complementing about this, according to the model :

       

    It seems shortcut to battery (SCB) situations are not modelled --  " Line transients do not match" -- , so I feel that what I see in simulation under SCB situation is not really what I would see in reality.

    At the end I wonder if as long as I meet the specifications about difference between Vin and Vout,  device will survive and should not worry about reverse current.

    For example, if my minimum input voltage is 5.5V, then during a SCB situation, I just must keep voltage at Vout pin below 45V, make sense ?

    Maybe there is new model prepared for this kind of situations in order I can have an idea of real reverse current in case of SCB.

    I see from this other forum TPS7B4254-Q1: OUT Short-to-Battery Protection - Power management forum - Power management - TI E2E support forums

    that basically this is the conclusion: I just must keep voltage at Vout pin below 45V

    In the other hand, I need to analyze protection for Vin in case reverse current, my concern in this case is the additional voltage drop.

    I appreciate your support for the ideas above.

    Br,

  • 0 in reply to Fausto Garcia
    TI__Expert 6450 points

    Hi Fausto,

    Regarding the long start-up of Vout, I was not able to replicate the same behavior in a circuit with only a load (without the battery portion). This additional portion of the circuit with the battery may be affecting the pspice model.

    Also, the line transient not matching would definitely affect you when simulating this type of scenario. As of now, I do not believe there will be a new model specific to TPS7B4254-Q1 for the short to battery behavior. However, I believe this portion of the datasheet might help understanding what happens during this event:

    You are correct that as long as you meet the requirements in the absolute maximum ratings the LDO should survive the short circuit to battery. If your Vout reaches 45V while Vin = 5.5V the absolute maximum rating is still met since IN-OUT = 5.5V - 45V = -39.5V. However, if you're able to lower Vout then you will be in a safer range for this LDO.

    The internal circuitry in this LDO should help in the case of a reverse current, since the back-to-back PMOS will shut down to prevent current from flowing out of the IN pin.

    Regards,

    Andres