TPS5130: PGout signal not behaving as it should

Got it, we will get back to you tomorrow.

Hi Russell,

It is really an interesting discovery. I also want to figure out what's going on. But I can't replicate this phenomenon in lab right now. Would you mind capturing the PG_Delay pin's waveforms with and without 8.2 nF cap ?

Hi Harry, 

Thanks for looking into this. :) 

I have added the captures below. 

8.2 nF cap on PG_delay

1. PG_delay starts ramping up 1 ms prior to the ramping of 3V3 and 5V2 outputs

2. it takes approx. 11 ms for PG_delay to reach termination voltage of approx. 2.2 V

3. PG is enabled when PG_delay is 1.2 V

PG_delay open

1. PG_delay goes high (approx. 2.2 V) at 1 ms prior to the ramping of 3V3 and 5V2.

2. PG ramps along with 3V3 as shown in captures previously. 

Ill look forward to hearing from you. :) 

Hi Russell,

1. Based on the waveform you captured, when PG_Delay has no external capacitor, the rising process of PGout should be divided into two stages (as shown in Fig.1). During the time t1 (PGout<~0.9V), the voltage of PGout is equal to '3V3', During t2 (PGout>~0.9V), the voltage of PGout is equal to '3V3'*10k/(10k+24.9K). As shown in Fig.2, and the same phenomenon occurs. The reason why this phenomenon exists may be related to the conduction voltage of the FET, and you can confirm it through the lighting time of the LED.

2. When PG_Delay has no external capacitor, it can be seen that PG_Delay rises to ~2.2V quickly, the internal TIMER completes the startup and then the TIMER turns off the back-end FET, so we can see the phenomenon in item 1. When PG_Delay is connected with an external 8.2nF capacitor, the current source inside PG_Delay will charge the capacitor until the voltage reaches ~2.2V. The internal TIMER has a soft start time. During this period, the back-end  FET  is always on(PGout = 0V) until TIMER completes start-up, then the FET is turned off, PG voltage rises to '3V3'*10k/(10k+24.9K).

3. In the datasheet, it has been mentioned that this is the  Programmable delay for Powergood. So I don't think it's a bug.

Hi Harry,

Thanks for the speedy response. but i believe there is still an issue. 

Fig 4. 

Figure 4 above shows the INV3 connected to the two comparators which feed the OR gate. so whenever either of these conditions is true: (0.85 V +/- 7 %) then PGOUT is enabled on the open drain output of the FET even if the delay is open. i.e No delay. Fig.5 below shows how INV3 is generated on the Feedback of 3V3. 

Figure 5

So according to the block diagram of figure 4, INV3 > (0,85-7%) when 3V3_FB > 3.06 V. This is when PGOUT should go high if no PG_delay is set.

I have attached a capture (Figure 6.) of INV3 below with 5V2 and PGOUT. (Excuse the no capture of 3V3 with INV3 but you can see the ramp on previous scope images provided)

Figure 6.

From the block diagram i am uncertain as to how the timer function behaves but i expect it to be inverting AND logic, not inverting OR. 

Does this sound correct to you?

thanks again for your input. 

Hi Russell,

It can be derived from the operating process of the voltage comparator. (HV, LV is below)

When INV3 <0.85-7%, HV = '0', LV = '1';  When 0.85-7%< INV3 <0.85+7%, HV = '0', LV = '0'; When 0.85+7%< INV3 , HV = '1', LV = '0'; 

If it is inverting AND logic, it doesn't make sense. You can confirm it again.

Let me know if you have any questions .

Hi Harry,

Sorry for the delay getting back to you. 

Yes i absolutely agree with that and i was trying to reason that in my comment above.. by "timer function" i meant the inverting timer block, not the whole PG circuit.... this however does not explain why PGOUT ramps with INV3 as shown in Figure 6.

PGOUT should only switch on once 0.85-7% < INV3 < 0.85+7% [0,0] i.e. when TIMER = 1. i.e FET is active, so PGOUT is pulled to ground due to open drain. so the logic is a little funky here for me. 

The above table shows that PGOUT is active when INV3 is out of bounds. 

Nontheless, It is still unclear why PGOUT ramps with INV3..?

I appreciate the feedback you have given.

Kind regards, 

Russell  

Hi Russell,

PGout and INV3 both ramp with 3V3, so the result looks like PGout ramps with INV3. The difference is that INV3 ramps with 3V3 through 3V3_FB feedback circuit, while PGout ramps with 3V3 through external LED driver circuit. You can verify this guess by disconnecting the PG Power Good circuit. 

Correct. But power good is defined as when the power is good. not when the power is ramping.

So ultimately the PGOUT signal should become active when INV3 reaches 0.85V (+/- 7%) (with no delay set)... which it doesn't.

Hi Russell,

we will discuss it and give you a feedback tomorrow, thanks!

Hi Russell,

Sorry for the late reply due to the epidemic in Beijing. We saw the same phenomenon as you in the lab and tried many tests. Regarding whether this is a bug, we need to confirm with the design engineer. Will give you a sure reply.

The question was closed because it went on for too long. However, we will continue to communicate with you until the problem is resolved.

Best Wishes.

Hi Harry,

Totally understand. We are still using the controller and just use the 8.2 nF for PGDelay to ensure that the power is good. However i am looking forward to the findings the TE lab finds.....

Hi Russell,

Due to the pandemic, many of my colleagues have been infected with COVID-2019. Thank you for your understanding and waiting...

Yes mate i understand. ive had it 2 times now. not a big deal but not very nice either. i wish all your colleagues a speedy recovery.

Thanks very much. We also hope to go back to the lab as soon as possible, and do more tests to give you a nice result.