TLC6983: How to calculate max frame rate ?

Hi JH,

Glad to help you. Somes points:

1. Max SCLK is 25 MHz, not 50 MHz. Please refer to Section 7.6 Timing Requirements from the datasheet.
2. You can refer to Section 9.2.1.2 SCLK Frequency from the datasheet to see an example that illustrates the estimation method between frame rate and SCLK.
3. You should also take into account the VSYNC command. Also, please check the bit length of ST and HB.

   jh lee said:

   I need total clock count = (ST+HB+1pixel DATA+END) * 16 channel * 16 line = (18bit + 16bit + 17*3bit + 18bit) * 16ch * 16line  = 26368 bit
4. I am very interested in your application. Could you share more information about the application if possible? What frame rate / refresh rate do you need? 

Best Regards,

Steven

Thank you for your reply.

I can see 9.2.1.2 . But I'm confused about x4 in "V_Data is 30 × 32 × 48 bits × 4 "  

and 0.8 in  "fSCLK = V_Data × fframe / 0.8" 

could you give me more comments about this?

======================================================================================

9.2.1.2 SCLK Frequency
The SCLK frequency is determined by the data volume of one frame and frame rate. In this application, the data
volume V_Data is 30 × 32 × 48 bits × 4 = 184.32 Kb, the frame rate is 120 Hz. Suppose the data transmission
efficiency is 0.8, the minimum frequency of SCLK must be: fSCLK = V_Data × fframe / 0.8. So the minimum SCLK
frequency is 13.83 MHz with dual-edge transmission.

======================================================================================

I need over 3600hz frame rate for 16x16 pixels.

Could you have any suggestions? 

Hi JH,

1. For "x4", it means there are four 30x30 matrices in one CCSI BUS. See below figure.
2. For "0.8", it is an estimated data transmission efficiency due to the need to transmit extra bits like start bit, head-bytes, check bit, end-bytes, VSNYC command, etc.
3. One thing to confirm: Is ">3600Hz" the refresh rate? Or the frame rate?

Best Regards,

Steven

I meant frame rate not refresh rate.

Can the CCSI bus have only one? 

Can I calculate like below?

14line x 16 pixel x 48bit x 1bus = 10752bit

10752bit x 3600 / 0.8 = 24.2Mhz with dual-edge transmission.

Hi JH,

1. Thanks for the confirmation.

2. Yes. You can have one device on the CCSI bus.

3. Why do you use 14line here? For 16x16 LED matrix, you should use 16line here.

jh lee said:

Can I calculate like below?

14line x 16 pixel x 48bit x 1bus = 10752bit

10752bit x 3600 / 0.8 = 24.2Mhz with dual-edge transmission.

4. If you are going to use >3600Hz frame rate, you cannot achieve high PWM resolution due to the short period of a frame. I am very curious about why you need such large frame rate. Could you share more detailed information if possible? You can contact me at steven-li@ti.com if needed.

Best Regards,

Steven

Hi Steven Li

3. I need a frame rate > 3600 Hz. 16 line can't meet SCLK spec. so I choose 14line not 16line.

4. PWM resolution 10-bit is ok for my application. If 10-bit is not possible then 8-bit would be fine. (can't control pwm period?)

   I can't tell you the specific but 3D display.

Hi JH,

1. I got your meaning. Do you have any requirements about refresh rate?
2. The minimum PWM resolution supported by TLC6983 is 11-bit. I did some calculation and I think theoretically 11-bit can work for your requirements.
3. PWM period (The total counts of PWM) can be adjusted with SUBP_NUM and SEG_LENGTH register field.
4. Remember the data transmission efficiency "0.8" mentioned above is just an estimated value. It actual depends on your real operating condition.

Best Regards,

Steven

Hi Steven Li

I really appreciate your efforts.

1. Actually refresh rate is not important but in my understanding, the refresh rate is the result of PWM ES-PWM operation. Isn't it?

    Anyway, my concern is frame rate not refresh rate. 

2. 3. So glad to hear that.

4. Let me get straight. " It actual depends on your real operating condition. " this is very confusing.  why can't calculate exactly? 

    You know what I need now, so could you give me an exact number ? 

   In My understanding, In 9.2.2.3 Figure 9-4 Data Write Flow,  when I need 14 lines then  I calculate 

    (2bit + 17bit + 17*3bit + 18bit) * 16ch * 14line   = 19712 bit ( 394us at 25Mhz with dual trans) 

    Is this right? can you check this exactly? the spec. is very confusing. 

   I think if you can give me that number or more specific documents then this resolving.

 Thank you.

Hi JH,

1. Refresh rate is related to DS-PWM. Actually, refresh rate = frame rate * SUBP_NUM.
2. Sorry for any confusion my words may cause. Let me make it clear. See comments below.

Steven Li said:

Remember the data transmission efficiency "0.8" mentioned above is just an estimated value. It actual depends on your real operating condition.

The data transmission efficiency depends on a lot of factors:

• What data you are going to send besides the grayscale data. Data transmission efficiency is primarily used to compensate for start bit, head byte, end byte, check bit, VSYNC command, or LOD/LSD readback, etc. (Because you can't spend 100% of your time sending grayscale data).
• How many devices you are cascading in one CCSI bus.
• The controller. Data transmission efficiency can be compromised if the controller is unable to transmit bits continuously.

Therefore, "0.8" is just an estimated value and the actual data transmission efficiency depends on your real operating condition. Normally at this stage, we can just do a rough estimation because the actual situation may differ from the theoretical situation and may differ from cases to cases.

Since you want a more precise estimation, I did a theoretical calculation for you. Sorry to find that the actual data transmission efficiency is much lower than "0.8" since you only have one device without cascading. From calculation, you can achieve max frame rate = 3.9796kHz@16x9 matrix and max frame rate =  3.582kHz@16x10 matrix. The detail for the theoretical calculation is shown below:

Suppose you just send the data and then send the VSYNC command, without LOD/LSD readback, for every frame, for one 16x9 matrix without cascading, and your controller can transmit bits continuously without a break, then the total bits you need for each frame is

bits_to_transfer_per_frame = bits_for_grayscale + bits_for_VSYNC

                                            = (ST + HB + Data + END) * 16-channel * 9-line + (ST + HB_VSYNC + END)

                                            = (1 + 17 + 3 * 17 + 18) * 16 * 9 + (1 + 17 + 18)

                                            = 12564 bits

And the max frame rate is

max_frame_rate = 2 * f_GCLK_MAX / bits_to_transfer_per_frame

                           = 2 * 25MHz / 12564

                           = 3.979kHz > 3600Hz

Best Regards,

Steven

Hi JH,

You are welcome. I am going to close this thread. If you have any further questions or concerns, please feel free to contact me at steven-li@ti.com

Best Regards,

Steven