TPS6594-Q1: CRC on Register Map

Hi Zhihua,

What OPN are you using? REG_CRC_EN is already enabled set as 0x1 by default on all released parts.

Thanks,

Daniel W

Hi，Daniel

I will check OPN setting. 

If REG_CRC_EN is set by OPN, is it necessary to set it again in SW? And will it lead to reset?

Thank you!

Zhihua

Hi Zhihua,

It is not necessary to set it again by software. It should not lead to a reset. What write are you making?

Thanks,

Daniel W

Hi Daniel

I just set GENERAL_REG_1.REG_CRC_EN = 0b1, to enable the register CRC. 

BTW, how to confirm that REG_CRC_EN is set by default? I read the register GENERAL_REG_1.REG_CRC_EN, it's 0b0 after power on.

OPN:  TPS659411F0RWERQ1 and TPS659413F0RWERQ1

Thank you!

Zhihua

Hi Daniel

I double check the OPN again, and sorry for that wrong information. Here is the OPN number: TPS65941212RWERQ1 and TPS65941111RWERQ1.

Regarding the register setting issue. I set the RUN_CRC_UPDATE to 0x2, and wait more than 2ms. The SW reset when it execute "GENERAL_REG_1.REG_CRC_EN = 0b1". 

Then I check the RUN_CRC_UPDATE  register to confirm that I write 0x2 successfully, but the register is automatically clear according to the data sheet.

So do you have some suggestion?

Thank you!

Zhihua

HI Zhihua,

Thanks for the update. Please read the interrupts after the software resets. This will help what the pmic is seeing. interrupt reading is described in the link below.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1112617/faq-tps6594-q1-lp8764-q1-debugging-pmic-behavior-with-interrupt-interpretation?tisearch=e2e-sitesearch&keymatch=tps6594%20interrupt#

Thanks,

Daniel w

Hi Daniel

According the suggestion in your replay. I checked the register INT_TOP, INT_FSM_ERR and INT_ESM after reset.

INT_TOP = 0x18, INT_FSM_ERR = 0, INT_ESM = 0;

For INT_TOP.  I check the register INT_MISC and INT_STARTUP.

The INT_MISC. BIST_PASS_INT and INT_STARTUP. ENABLE_INT is set. I don't find anything strange. 

Any advise?

Thank you!

Zhihua

Hi Zhihua,

If the register CRC check was causing the reset, I would expect to see REG_CRC_ERR_INT as well.

The 2 interrupts listed just show a clean startup. Can you monitor the pmic outputs to see if they go low when you see the software reset?

Thanks,

Daniel W

Hi Daniel

As INT_TOP.MODERATE_ERR_INT is not set, so I assume that REG_CRC_ERR_INT is also not set. But I check that the reset status of REG_CRC_ERR_INT is 0. So suppose that a shut down sequence happens because of CRC error, can we get the REG_CRC_ERR_INT set after reset?

Which PIMC output shall I check, nINIT pin?

Thank you!

Zhihua

Hi Zhihua,

If VCCA is not cycled, REG_CRC_ERR_INT will remain latched if it causes a shutdown. From the interrupts it appears that the pmic does not reset. Please take a scope shot of VCCA and TPS65941213 BUCK 1 and 4 when the software resets.

Thanks,

Daniel W

Hi, Daniel

Sorry for some error information above. I find some mistake in the test step to read the error register. (INT_TOP, INT_FSM_ERR..), the test environment will also power off the PMIC if SW reset. So I adjust the test environment to keep the power supply and do the test again. Then the reset reason is CRC mismatch!

So if CRC on register is enabled by default, why it has impact when I set GENERAL_REG_1.REG_CRC_EN = 0b1,  why not at early time?  If it is not enabled by default, shall I calculate the CRC at the end of initialization phase and then enable the CRC check?

Could you give me some advice?

Thank you!

Zhihua

Hi Jari

Thanks for the information.  Let me explain the background.

At first, I don't know the REG_CRC_EN is set by default. So I try to enable this feature by set REG_CRC_EN = 1. But the SW will reset immediately after I set the register. So I raise this ticket. And suggested by Daniel (refer to the discussion above). I want to confirm this feature is enabled, so I read out the REG_CRC_EN, but it is 0.  So I am a bit confused and not sure if it is really enabled. Also I check with Daniel, even I set the REG_CRC_EN to 1 again, it will not lead to reset. 

After discussion up to now, I still confuse about 

1. As REG_CRC_EN is enabled already, why REG_CRC_EN readback is 0?

Thank you!

Zhihua

Hi Zhihua,

If REG_CRC_EN is read as "0" this means that samples on the board cannot be TPS65941212RWERQ1 or TPS65941111RWERQ1.

There must be some other explanation to this. Could you be able to read registers 0x1, 0x2 and 0x3 from both devices? These registers will tell the default NVM configuration.

BR, Jari

Hi, Jari

We read out the register content as below

Register 0x1 is 0x82

Register 0x2 is 0x12

Register 0x3 is 0x02

Thanks!

Zhihua

Hi Zhihua, 

Daniel our TPS6594x-Q1 expert is out of office today. Please expect a reply within the next two business days. Thank you for your patience. 

Regards,

Garrett 

HI Zhihua,

Please read the same registers for the TPS65941111 pmic as well. Register 0x3 shows that these devices are an old revision. Most up to date revision is 0x3. Both Rev2 and Rev3 appear to have REG_CRC_EN as 0x1 default (Register CRC Enabled).

Thanks,

Daniel W

Hi Daniel

The register content of another PMIC chip is as below

Register 0x1 is 0x82

Register 0x2 is 0x11

Register 0x3 is 0x02

So that means both two chips are Rev2, and REG_CRC_EN is 0x01 as default, is that correct?

Hi Daniel

Thank you for the confirm. 

I still worry about that maybe I change the register somewhere as I read out the REG_CRC_EN is 0.  Is there any fault injection test that I can try to verify the feature is enabled? Eg, I change some register content?

Thank you!

Zhihua

Hi Zhihua,

Please try writing 0x10 to register 0x3E and then read the interrupts on the pmic.

Thanks,

Daniel W