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TPS37AQ1EVM: Output reset latching feature

Anubha Gupta
Intellectual 1460 points
Part Number: TPS37AQ1EVM

Hello team e2e, 

I have a question regarding the "Output reset latching feature”, but it is not clear to me how to use it. Is it possible to latch the RESET output once an undervoltage is triggered. I mean keep the output “active” even if the sensed voltage goes back to nominal; and de-latch it only when commanded with a digital signal from MCU?

Is it via the Manual reset (MR) pin that this trigger can be sent via MCU ? My understanding is that if we connect a 10uF cap at MR pin, the programmable delay time can be set to max i.e. 1.28s, hence the RESET signal would be sent by MCU after 1.28s, is that correct ? 

Also, acc to this MR functional table : 

What happens if you keep the MR pin low ? What is "reset asserted" 

Thank you,

Anubha

  • 0
    TI__Mastermind 18320 points

    Hi Anubha,

    The latching feature works such that when the RESET pin is low (asserted), it will not go high (deassert) until a predetermined voltage (please see electrical characteristics on page 8 of data sheet) is reached. This means that the RESET pin can be kept low (Reset asserted) by holding the MR/CTR pin low.

    Thanks,

    Patrick