BQ76952: Some question about BQ76952

Hello Gabriel,

1. The pre-discharge logic delay is not controllable. When the predischarge is on, the primary discharge will wait for 240ms. Sometimes, the primary discharge will not turn on until the predischarge is off. This is because the current I2C communication rate seems to be related.
How long until the DSG pin is enabled after PDSG will depend on the PDSG settings. I don't believe it should wait 240-ms. But I don't understand what the question here is.

2. The RTC resets the initial time. After the sleep test, it is found that the RTC time is sometimes reset to the last backup time, that is, the time is naturally inaccurate, which may be related to IIC communication and RTC policy.
I don't quite understand this question. Could you clarify?

3. The equilibrium is off for a long time. After the equilibrium is on, the time to close the equilibrium is more than 2S, and the measured time is 2.5S.
Is this a question or a statement? What is the question?

Best Regards,

Luis Hernandez Salomon

Dear Luis

BQ7695202PFBR chip Our core problem is:
1, the chip's I2C communication to obtain voltage, current, temperature and other information, communication failure rate is high.
2. Communication failure leads to repeated communication and increases the latency of the underlying interaction.
3. Communication failure leads to large response delay and increased uncertainty of MOS switches and other actions.
4. The voltage of the single cell obtained during the start of equalization fluctuates greatly.
5. Slow response time to stop balancing.

Hello Gabriel,

Can you describe exactly what communication failure are you seeing? Do you have any examples or logic analyzer images? Does your MCU support clock stretching? 

Can you share your schematic so I can review it? If you are getting inaccurate cell measurements during cell balancing, it is possible that the time constant of the input filter is too large, so it may need to be decreased.

This e2e thread may answer some questions about the cell balancing timing: https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/967073/bq76952-bq76952-cell-balancing-questions

But in short, the balancing time would depend on your configurations, if you can share your .gg file I would be able to see what you chose.

Best Regards,

Luis Hernandez Salomon

Dear Luis

1) Please provide the delay data of discharge MOS from off to on;

2) We used the discharge control pin or made the chip output discharge MOS control through communication commands, but there was a large time delay. This delay does not meet our practical application requirements;
The influence of communication and delay of chip MOS signal driver output to actual MOS driver have been excluded.

3) Attached DFETOFF control discharge MOS waveform, which can be viewed by DSView software;2626.Waveform.zip

BQ7695202-SCH Protel Schematic.pdf

Hello Gabriel,

1) Please provide the delay data of discharge MOS from off to on;
From off to on can take up-to 250-ms. The device will determine if it was told to turn-on the FETs every 250-ms. This is mentioned in Section 6.9 Device Event Timing of the Technical Reference Manual.

2) We used the discharge control pin or made the chip output discharge MOS control through communication commands, but there was a large time delay. This delay does not meet our practical application requirements; The influence of communication and delay of chip MOS signal driver output to actual MOS driver have been excluded.
Is this delay only during turn-on? If so, it is because of the reason above. If using commands or de-asserting DFETOFF, it would take up-to 250-ms to turn-on the FETs. 

The schematic looked fine to me. Would just suggest that the ESD components, like C38/C39 should be going around the MOSFETs, so from the source of the CHG FET to the source of the DSG FET. You want to create a low-impedance path around components so that the ESD current can reach the battery of the cells.

Best Regards,

Luis Hernandez Salomon