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UCC28950: Recommendations for slave SS capacitor

Iain Davis
Prodigy 110 points
Part Number: UCC28950
Other Parts Discussed in Thread: PMP6712

Hello,

Regarding the selection of the SS capacitor value for the slave controller.

The Datasheet states: It is recommended that the SS on the master controller starts before the SS on the slave controller

Would you recommend staggering the EN signals, and/or increasing the value of the slave SS capacitor?

How best to set this timing? i.e. ensure the slave starts after ~10 clock cycles on SYNC pin?

Lastly, the SS capacitor sets the cycle-by-cycle current duration (& hiccup mode off-time duration) - would this imply we'd want the master * slave SS capacitors to be closely matched?

Thank you in advance,

Iain

  • +1
    TI__Mastermind 23545 points

    Hi Iain,

    Thank you for the query on UCC28950.

    You might want check to check PMP6712 where similar capacitors are used for master and slave controller as shown below:

    https://www.ti.com/lit/df/slura08/slura08.pdf?ts=1669184440322

    But I can recommend is to stagger the EN signals, but the problem is that for the Master sync pulses start after SS pin reaches 0.55V threshold. But the slave can start generating voltage on the SS pin even though sync pulses are not received. So you might also consider slightly increasing the capacitor here so that master converter must reach its enable threshold voltage before SS/EN on the slave converter starts for proper operation. Once this is finez, you can try optimizing the SS capacitor for cycle by cycle current limits.

    Regards,

    Harish

  • 0
    Prodigy 110 points

    Hello Harish,

    Thank you for very much for your insight (& providing PMP6712 schematic!!) - very helpful.

    Regards,

    Iain