LM7310: Unexpected Latch-off condition

In the oscilloscope screenshot, the magenta is the Vin; the yellow is the Vout.  The other signals are not related to the LM73100.

Hi Michael,

Can you check if it is replicating with single LM73100?

Regards

Kunal Goel

Hey Kunal,

We tried two different scenarios to test this. 

1) We disabled the output supply going to the Vin pin of one of the two LM73100's which keeps one of the two LM73100's powered off.  We could still get the LM73100 that was still powered to latch up.

2) We left both LM73100's connected to their respective 3.3V supplies.  But on one of the LM73100's we strapped the EN/UVLO pin to ground which should keep it disabled.  We were still able to get the other LM73100 to latch up.

As additional information, when we have the LM73100 latched off, we were able to get it to recover just by touching the EN/UVLO pin with an oscilloscope probe.  If we kept the oscilloscope probe on the EN/UVLO pin, we could not get the LM73100 to latch off.  So we thought - perhaps a little capacitance is needed on the EN/UVLO pin.  So we added a 4.7pf capacitor from the EN/UVLO pin to GND.  We could still get it to latch off, but in this case, touching the pin with the oscilloscope probe would not allow it to recover.  

All of this got us to thinking if we really need to use the UV feature.  So we removed the center resistor in the triple resistor chain that controls the UV and OV setpoints.  This effectively tied the EN/UVLO pin to VIN and the OVLO pin to GND.  In this configuration we could not get the LM73100 to latch up.  So we are hoping tying the EN/UVLO pin to VIN might be a solution for this problem assuming it is just the EN/UVLO pin causing the problem.  Long term we still need the OVLO feature enabled.  We have not tested UVLO disabled and OVLO enabled just yet.  That is on our list for today.

Thanks

Mike

Hi Mike,

1. Can you share your schematic?

2. What is the load at output during test?

3. Please share waveforms for all cases you have tested showing VIN,VOUT,EN,IIN in both us scale and ms scale. Lets focus on region when UV event happens.

4. Also one thing to try. For the three resistors in resistor divider case if you pull down EN pin externally and then release does part turns off and recover?

Regards

Kunal Goel

Kunal,

Here is our schematic.  There is an additional 70uF at the FPGA that this rail powers.  In addition, there are seven filtered supplies off of +3V3_FPGA that are behind a 1 ohm resistor that each have a 22uF capacitor.  So this is basically an additional 154uF of capacitance on the +3V3-FPGA rail.  

I am not sure of the load current the FPGA is pulling when the brownout condition occurs but it should only be a few hundred milliamps.

The above in blue and magenta are the 3.3V supplies connected to the two LM73100 inputs.  Green is inrush on my main power bus but not really relavent to the issue at hand.  The yellow signal is my trigger which is the enable of a bunch of other sub-systems which cause the inrush that downstream causes the two 3.3V rails to droop as shown.

The above blue trace is the output of the two LM73100s.

In the above snapshot, blue is the droop on my main power bus that then causes the droop on the 3.3V supplies (one of which is shown on the magenta trace).  The yellow is the output of the two LM73100s.  Green is my FPGA reset being asserted by the brownout detector monitoring the +3V3-FPGA power rail.

Last image that I have to share right now.  Green is the FPGA reset signal used to trigger the scope.  Yellow is the +3V3-FPGA power rail (the output of the two LM73100s).  Magenta is the IMON pin of one of the LM73100s.  The blue signal is not important to the issue we are discussing.

The answer to #4, is yes.  If we pull the EN pin to GND and release it, the LM73100s do recover.

Thanks,
Mike

Hi Mike,

I am out of office till 8th Dec. I will get back to you by Friday.

Regards

Kunal Goel

Hi Mike,

Please share your email id. Lets follow up on mail. I have a theory what could be happening.

Regards

Kunal Goel