Hello,
When turning on the board, GATE pin comes out and MOSFET V1175 is on.
UVLO shows high, OVLO is low, Voltage on MOSFET is 0.15V. PG has 10V pull-up with 5kohm.
A Question is PG show low.
What condition makes this is possible?
Please advise me.
Regards,
Moon
Hi Moon,
Thanks for reaching out to us. Please sharer the complete schematic. I am not able to understand the power good pullup circuit in your schematic.
Please note that the source of open drain MOSFET implementing the power good is connected to VEE. This requires special attention on the implementation of power good pull up circuit. A isolator need to be used. Please refer to the EVM schematic in AN-2143 LM5064 Evaluation Kit (Rev. B).
