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TPS7H1101A-SP: EN to PGOOD turn off time

Matty13763
Intellectual 440 points
Part Number: TPS7H1101A-SP

Hi,

I was wondering if you knew the time it will take the PGOOD signal to go low once the EN is low.

I need this PGOOD signal low before other enable in my sequencing of converters in the power off stage and wanted to ensure PGOOD was low before other devices get turned off.

Thanks!

  • 0
    TI__Guru 62930 points

    Matty,

    We do not have a specification for this.  This is predominately due to the fact that the PG de-assertion is based on the Vout threshold, and not directly dependent upon EN state.

    PG will de-assert when Vout is below 86% of programmed Vout.  Or worst case would be 84%, if you include the 2% hysteresis.

    How quickly Vout collapses will be dependent upon your output capacitance and the load.

    The regulator will disable the pass transistor very quickly after enable is de-asserted.   I don't have a spec'd value for this, but it should be within the same timing as E prop Dly.  This is worst case 1mS.

    If this answers your question, please click this resolved my question.
    Regards,
    Wade

  • 0 in reply to Wade Vonbergen
    Intellectual 440 points

    Hi Wade,

    Thanks for your response. So from your email:

    1) EN going low doesn't really affect PG signal directly. EN going low will cause Vout to drop and when at 84% or so, then PG will go low. I need to determine how fast that Vout will fall.

    2) Soft start pin has no effect on power down only power up

    2) I can assume that once EN is de-asserted, then Vout will start dropping around 1ms later (for my calculations I can assume 5ms and I am still fine)

    Does this make sense?

    Thanks!

  • 0 in reply to Matty13763
    TI__Guru 62930 points

    You are welcome.

    1) Yes.

    2) Correct

    3)  I believe this to be valid.  However, I will test this in the lab this afternoon and reply back.  I can put a large load on the LDO, and measure the time from EN to start of Vout falling.  

    Regards,

    Wade

  • 0 in reply to Matty13763
    TI__Guru 62930 points

    Here are 2 plots for reference.  One enable, and one disable.  Plots include Vout, EN, and PG.

    This is with a stock EVM and 1.5A load.   Cout is 226.6uF

    Hopefully this gives you enough data to calculate your supply timing.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Intellectual 440 points

    Thanks Wade.

    So for the power down picture, I am seeing

    1) EN goes low

    2) Approx. 16us later, PG goes low based off Vout being 86% or lower of Vout (so around 1.55V)?

    If that is so, it is hard to tell when Vout drops that low, but if my assumptions are correct, it looks like PG goes low pretty quickly after this for the setup you have.

    Does this all seem reasonable?

  • +1 in reply to Matty13763
    TI__Guru 62930 points

    Matty,

    yes, I agree with your assessment.

    Keep in mind the PG threshold of 86% is worst case. Typical is 90%.    I should have changed the vertical scale for Vout, so it would be a little easier to see its drop relative to PG de-assertion.

    It might be better to think about this as the LDO stops passing current ~10-20uS after EN goes low.

    You should be able to estimate how fast Vout decays with your capacitance and load and keep enough margin to insure your sequence is correct.

    Regards,

    Wade