1. due to some reason, can they connect AGND to NC first and then use NC pin to connect to thermal pad?
I assume NC doesn't connect to anything so should be flexible, right?
2. there's a conflict there, pin definition said don't connect anything to DRTN but layout example says differently,
please guide us the right direction
3. regarding power sequence, can AVIN power up before PVIN if these two are separate ?
Hi Peter,
here's their layout,
as you can see the AGND PGND connection is one 0ohm,
1.so actually AGND is connect to 0ohm through a "Via" first, and then through multiple vias back to thermal pad, do you think this is acceptable?
2. they want to add extra three 0ohm parallel, do you think it's necessary or helpful?
Hi Peter,
1.as you recommended, use a 0ohm to connect AGND pin and AGND net, but most of area of AGND plane is in layer 3.
please check
2.please check the Cout placement
as you can see, still two MLCC are in bottom side (six at top) due to the area constraint.
and the SW area is reduced.
although I think the layout is alright to me,
I would still recommend you take a glimpse on one of a TPS546D24A layout,
don't have to check every TPS546D24A.
after all they use nine pcs per board, it's better double check. thanks
Some recommended improvements to the layout
1) Move the high-frequency bypass capacitor on the back-side of the PCB under the PVIN pins and add some additional PVIN vias as close to the PVIN pins as design rules allow. This keeps the loop of the PVIN bypassing in the plane of the board and offers better switch node ringing reduction.
2) Expanding the back-side PGND copper area beyond the device will also help with thermal dissipation to the ambient air, reducing device operating temperatures
3) There appears to be a component between AGND and PGND at the AVIN and VDD5 bypassing capacitors. The only connection from AGND to PGND should be mounting surface connection from the AGND pin to the exposed thermal pad.
This resistor should be connected between the AGND island and the AGND pin, not between AGND at the AVIN bypass capacitor and GND at the VDD5 bypass capacitor. This configuration will introduce a lot of PGND noise between the AGND net and the AGND pin.
Looking through more of the layout, it looks like there are more AGND to PGND resistors spread through the layout, creating significant ground loops between AGND and PGND, which could further interfere with device operation. There should only be 1 single-point connection between PGND and AGND, and that single point connection must be the direct connection from the AGND pin to the exposed pad.
It would be better to connect the AGND to PGND resistor directly to the AGND pin rather than connecting the AGND to PGND resistor to the NC pin, and then the NC pin to the AGND pin through the Exposed Pad. This will minimize PGND noise between the AGND pin and any AGND components.
Hi Miller,
would you suggest these MLCC move to left side and parallel with four POSCAP since the loading is on the left?
the location of MLCC right now is at the rightmost side of the board , just want to know if this concern you?
Hi Miller,
sorry about that,
I understand the theory but as you can see , it's hard to put remote MLCC close to the load,
but I'll ask them to move half of the MLCC to the left side and maybe closer to the load as possible,
but I wonder why bottom side also, the inductor is at top side, so go through bottom is supposed to have some parasitic (vias)?
