LM5085: Poor load regulation, and premature current limiting

So I increased the value of R4 (Radj), and that seems to have helped the current limiting issue, however the load regulation is still very poor. Vout should be 44 V, but at a 3.5 A load, Vout is 41 V. At 4 A, Vout is 38 V. At 4.5 A, Vout drops way down to 30 V. At 5 A, Vout is 28 V.

The regulator is not keeping FB at 1.250 V. Even at a relatively paltry 0.5 A load, its at 1.205 V. By the time the load gets to 2 A, FB is 1.177 V, by 3 A, FB is 1.095.

I probed the gate signal, and it looks like the duty cycle is about 90% throughout the entire load range (with Vout set to the maximum value). This regulator should be capable of 100% duty cycle, but it doesn't seem like it is in order to bring FB back up to 1.25 V. Ohmic losses across the Rsens, Q1, and L1 don't account for the marked drop in Vout (also, those would be linear).

My gut is telling me that the issue is with C3, C6 and R10, but I'm not sure what to do.

Thank you!

I guess the numbers that I used to calculate the values for C3, C6 and R10 would probably help you.

VA = Vout-(0.65*(1-Vout/Vin)

Vout = 46 V, Vin = 48 V

VA=45.97V

fsw = 712 kHz (I measured this at about 694 kHz, so it's not far off)

ton = Vout/(Vin*fsw) = 1.34 us

R10*C3 = (Vin-Va)*ton/delV

delV = 0.025

R10*C3 = 109e-6

R10 = 22 kO

C3 = 4.96 nF, rounded down to 4.8 nF

One thing I will note is that there is very little voltage ripple. I'm not sure whether that is relevant. I've also attached a screenshot with the gate signal.

Hi Tim,

Unfortunately we need a variable power supply, and this was the minimum number of resistors that would give us the range and sensitivity that we require. I'm using a mechanical potentiometer for the prototype, but the final design will use a digital potentiometer, which is much smaller than a mechanical one. The output plane convers the right and bottom side of the board (you can see it on the top layer).

Reducing the switching frequency would require an extremely large resistor. I can put a 1 MO resistor in place of the 430k, which would bring the frequency down to 300 kHz.

I probed FB, and the noise doesn't seem to be a function of load, although it isn't small. I've attached a screenshot.

I'll try bringing the switching frequency down.

I did make an interesting observation. I set the load to 5 A and rotated the potentiometer to get the lowest output voltage. At that load, Vout increased as I rotated the potentiometer until it was nearly at its extreme, when it dropped suddenly. That does not sound like a noise problem, but I don't know what it does sound like.

Hi Tim,

The bottom plane is a solid ground plane. I think we can deal with higher current ripple, although I'll look into other inductors. Earlier today, I switched out Rt with a 4.7 kO resistor. That raised the current limit to 5.2 A. I switched that out with a 6.8 kO resistor in hopes to bring it up even further. Much to my surprise, the current limit didn't change. It still shut off at 5.2 A. Do you have any insight as to how I could increase the current limit? Would I need to decrease Rsense? Given that I don't really care about current limiting, could I replace Rsense with a 0 O jumper?

Thank you!.

Hi Tim,

I'll do that right now. The VIN cap (C7) and VCC cap (C2) are very close to the IC. Rsense is a bit further away, and unfortunate necessity.

At a load of 4.8 A, the voltage across Rsense (R5) was 49 mV. The voltage between Vin and ISEN was 50.2 mV. It seems as though this may be the issue. As I said, I don't really care about current limiting. I could double up R5 to make it 5 mO.

I doubled up Rsen to make it 5 mO, but the current is still cutting off at about 5 A. The voltage between Vin and Isen is now 25.2 mV (surprise, surprise), so it should not be cutting off.

Moreover, I've noticed that it will cut off if I go from 0 A to 4.5 A (or higher) in a single step. This is a huge problem, as we will be modulating the load. Is this inrush current to the inductor?

I set up probes across the sense resistor and did a difference operation. There are a lot of transients, but the waveform did not change substantially as I changed the load. I've attached the screenshot.

I also made another very peculiar observation. I was able to get the load up to 7.5 A, but only when I was probing the gate of the FET. Similarly, I was able to jump from 0 A to 7.5 A, but only when I was probing the gate of the FET. What is your take on this?

Hi Tim,

The Rt and Radj resistors are close to the IC. There is a 1 nF cap on the ADJ pin. I could easily put a cap in parallel with Rt, say 100 nF? The SW node copper is fairly large. When I respin the boards, I'll implement those changes. The gate drive trace is only 8 mil, so I'll make it larger. I take it that's why the design worked when I was probing it with an oscilloscope.

I'll start with a cap at Rt and get back to you.

Thank you!

So I put a 100 nF capacitor in parallel with Rt and I was able to get up to 7.2 A, and I was able to load it from 0 A to 6.5 A without issue. I gave my self ample wiggle room because are a lot of unknowns about this project (believe it or not, it's equipment for vaccine production), but by my calculations (again, a lot of unknowns), we should only need up to 41.6 V and 6.3 A. I'll validate it with my existing prototype. Thanks for your help!

Peculiarly, now it seems to only work at Vout max. At any voltage less than that, it cannot regulate at even a small 100 mA load, unless I'm probing the gate. It seems as thought the narrow gate trace is the primary problem. I'm almost wondering if I should bounce it to the bottom layer. What do you think?

Also, because I like understanding things (and you seem to know things), and I'd like to explain this to my team tomorrow, why does the gate trace benefit from being wider, and what did probing the gate trace do?

Hi Tim,

Something went awry and I spent two days hunting down what turned out to be a cold solder. I added a 220 pF capacitor between RT and gnd (I didn't have 100 pF), and it didn't make any difference. I also had one of our technicians solder a wire between the gate of the FET and pin 6. It's not ideal, but it should reduce the inductance. This also did not make a difference. I also replaced C3 with a 8.2 nF cap, and R10 with a 18.2 kO resistor. This actually helped somewhat. So here is where things stand now:

1) Load regulation isn't fantastic. Vout climbs with the load. At mid-load, Vout can be as much as 10% higher than at no load. I'm guessing this has to do with noise at FB. I didn't think that this would be a problem for our application, but I ran it with our giant LED array, and it is not finding a stable operating point.

2) Current limiting is peculiar. If I probe the gate with an oscilloscope probe, it works perfectly. If I don't, it's better than it was originally, but not much better than before I operated on the board.

I made some changes to the next revision of the PCB layout:

1) Wider gate traces

2) Added footprints for caps to ground from RT and ADJ.

3) Added a footprint in series between ISEN and the low side of the current sense resistor.

4) Removed power planes from beneath the digital circuitry, instead connecting them with a trace.

5) Changed the input and output caps to ceramic.

6) Increased the value of the inductor

Some questions:

1) I popped the gate trace onto the bottom layer. I know vias increase inductance. Will this be a problem?

2) Do you think a choke between Vin and Rt, Radj, and Cadj may help?

3) Do you think a choke between Vout and Rfb may help?

4) Might a small bypass capacitor at FB be in order? There is still a lot of high frequency noise there.

5) Why does the oscilloscope probe at the gate help the current limiting? Electrically, what does it do?

6) Why do you suspect the voltage regulation is as poor as it is?

Thank you, and happy holidays!