Other Parts Discussed in Thread: UCC28070
Hi All.
What does IRIPA, IRIPB and F_KHZ pin in UCC28070 Transient model represent?
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Hi All.
What does IRIPA, IRIPB and F_KHZ pin in UCC28070 Transient model represent?
Hi,
Thank you for the query on UCC28070.
IRIPA, IRIPB, F_KHZ are additional pins added to the average model of UCC28070. F_KHZ pin generates the value of switching frequency. This value is taken as input to BOOST_AVG module for some internal calculation. BOOST_AVG module contains the average model implementation of Boost output stage. Similarly BOOST_AVG module generates peak to peak inductor current ripple (IRIPA/IRIPB) value through IRIPX pin which is used in UCC28070.
For running simulations, these pins cannot be left unconnected. I would request you to always connect F_KHZ pin of the UCC28070 to K_KHZ pin of BOOST_AVG module. Same connections are needed for IRIPA/IRIPB as well.
Regards,
Harish
Is there any document to understand the simulation design carried out in web bench?
Hi Aradhya,
There is no document to go through simulation. Please feel free to download TINA model and the refer the following application note https://www.ti.com/lit/an/slua479b/slua479b.pdf?ts=1672737663435&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FUCC28070 for choice of components.
Thank you
Regards,
Harish
Hi Harish,
Thank you for the design document. In Page 4, the statement after equation 7 states that the boost inductor value swings from 140 uH to 350 uH. Is the swing due to load variation. If yes could you please help me know the range of the output power variation?
Hi Aradhya,
This is not due to load variation.
Most magnetic inductance values change with DC current. In most cases they change 2:1 or even 3:1 and it depends on the magnetics manufacturer. Hence an avg. value is used for current loop compensation. PFC will regulate the output voltage to 390V and output power variation can be from no load to full load depending on the load resistor. Change in inductor is only going to vary the inductor current ripple.
Regards,
Harish
Hi Harish,
Can you please help me understand the PWM ramp added to the current signal for improving noise immunity.
Hi Aradhya,
Please refer to the following thread which discusses about this benefit.
Regards,
Harish
Hi Harish.
Thank you so much for your earlier response. I have few query listed below. Please help me to understand.
In the document "UCC28070 300-W Interleaved PFC Pre-Regulator Design Review", page number 7, I could not follow "A factor of 0.9 was multiplied by the current sense signal to leave room for the 10% PWM ramp that is used to make this design more noise immune at lighter loads.". Even I did not get proper answer in the link provided by you?
Secondly, there is no reset circuit in the primary side of the transformer. Is it not going to give rise to huge voltage spike across the primary winding when device is turned off?
Thirdly, to reset the transformer in a short duration the reset resistor should be as low as possible. But the equation (26) suggest otherwise.
Hi Aradhya,
Please find my reply below:
1. For you first query on noise immunity part, when the input voltage drops to very low values around the zero-crossings of the AC line cycle the inductor current will ring with the Coss of the boost mosfets. The effect of the ringing is to bring the starting point of the current waveform below zero at the start of the boost mosfet on-time. Because the current starts from a negative value this portion of the current will not be sensed by the CS transformer circuit as it only rectifies current which flows from drain to source in the boost fets, current in the positive direction, above 0. A small DC bias is added to ensure that the current sense signal is always above 0 so the true value of the current is sense by the CS transformer circuit. A ramp signal can be added to the CS signal during the on-time of the boost mosfets and is designed to increase the current sense signal magnitude to give a larger signal to noise ratio at light loads.
2. Please refer pages 32,33,34 of the datasheet for the recommended type of reset circuitry. You might also refer to the 6th/7th response in the following post which explains about CT reset process.
3. For proper reset of the magnetic core:
Von * D(max) = Vreset * (1-Dmax)
Vreset = Von *D(max)/(1-Dmax)
So at max duty cycle you can get a very large voltage across the rectifier diode and the diode needs to be rated for this.
The app note recommends a 100:1 ratio between the reset and the load resistors in order to limit the reverse voltage to 100 times theforward bias voltage of the transformer. This should occur at max duty cycle , D = 0.99
Please use the above recommendations.
Regards,
Harish
Hi Harish,
I still find the answer to my question as to how to reset the primary side of the transformer.
Moreover, when the switch is turned off, the primary current goes suddenly to zero. Why then it will try to maintain the secondary current as given in the statement "If there is no resistor on the output of a current transformer, a very large voltage will be generated as the primary current tries to maintain a secondary current equal to Ipri/N"
Hi Aradhya,
I am not sure on the author's intent but probably he is referring to avg. current.
Regards,
Harish
Hi Aradhya,
Can you please check the following links on CT reset methods in addition to the ones discussed in the datasheet:
https://www.napier.ac.uk/~/media/worktribe/output-231430/mcneillpdf.pdf
All of the above have reset circuits as we discussed earlier.
It would be helpful if you can share the schematic/block diagram of primary reset circuit which you are mentioning.
Regards,
Harish