Hello Team,
Posting on behalf of customer:
Essentially, I’m trying to do some worst case analysis that used the TPS3808 with a 33nF set capacitor.
I am using the datasheet’s equation (CT (nF) tD =[ (s) – 0.5 × 10- 3 (s)]× 175) and looking at my capacitance over temperature and tolerance.
Is this the most accurate way to model the timer delay output?
I ask this because looking at section 6.6, td RESET delay time, there seems to be about a ~40% variance in output with the Ct values. Should this variance be added into the calculation or was this just variance in the test conditions?
My initial assumption is that the equation with varying capacitance is the best way as the internal circuit is controlled with a precision 220nA current source and 1.23V reference. I can’t see 40% variance based on the device. Additionally, Figure 3 looks very linear over temperature, show casing the device robustness.
Regards,
Renan
