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Original question:

TPS650864: Pin setting when BUCK 6 and VTT is not used

TPS650864: TPS65086470

Ulas SAHIN
Prodigy 10 points
Part Number: TPS650864
Other Parts Discussed in Thread: CSD87381P, TPS3808

I plan to use TPS65086470 with Artix-7 but I am quite confused about how to use it,especially its CTL pins. As I understand from its datasheet, thanks to its OTP property, we dont need to do anything about its integration with Artix-7 and about the power sequence. Is this right?

Below shows my configuration and I believe that this configuration is already embedded in the TPS65086470.

Input=LDO5 /// BUCK_1 + CSD87381P => 1V0 for VCCINT

Input=LDO5 /// BUCK_2 + CSD87381P => 1V8 

Input=External 5V0 /// BUCK_3 => MGT1V2

Input=External 5V0 /// BUCK_4 => VCC_2V5

Input=External 5V0 /// BUCK_5 => VCC_3V3

Input=LDO5 /// BUCK_6 + CSD87381P => VCC_1V35

Input=BUCK_6 /// VTT_LDO => VTT_0V675

LDOA_1, LDOA_2, LDOA_3, SWA_1, SWB_1, SWB_2 => NOT USED //// I believe PVINLDOA2_A3, PVINSWA1, PVINSWB1_B2 should be connected to GND??

For the above configuration, what should I connect the CTL pins? In the evaluation board, all CTL pins have pull-ups and also connection to GND through a switch.

Best regards,

Ulas.

  • 0
    TI__Mastermind 31840 points

    Hi Ulas, 

    You are correct that the configuration you desire is already preprogrammed in the TPS65086470. For future reference the device comparison table on page 5 of the datasheet shows the default output voltage for each regulator. 

    Ulas SAHIN said:
    thanks to its OTP property, we dont need to do anything about its integration with Artix-7 and about the power sequence. Is this right?

    The TPS65086470 is specifically configured to power a Xilinx Artix 7. I still recommend double checking if the power up and power down sequences meet your requirements. These diagrams can be found on page 40 and 41 of the datasheet. 

    Ulas SAHIN said:
    I believe PVINLDOA2_A3, PVINSWA1, PVINSWB1_B2 should be connected to GND?

    Yes these pins can be connected to ground since they are not used. 

    For the CTL pins if you wish to have the full enable/disable functionality then you will want to design something similar to the evaluation board to allow CTL pins to be connected to either a pull up supply or GND. If you wish for outputs to be enabled at all times then you can simply connect the relevant CTL pin to a pullup rail in the range of 1V-3.3V.

    Best Regards,

    Garrett  

  • 0 in reply to Garrett Kreger
    Prodigy 10 points

    Hi Garrett,

    Thanks for your reply.

    If you look at the datasheet page 39, figure 8-15 "TPS65086470 Power-Up Sequence", I see that only CTL1 and CTL2 have the control for Artix-7 configuration but I do not need to connect these pins to a control circuit since TPS65086470 already does the configuration job by itself. Is that correct?

    What I understand is that the pulling-up of CTL pins does not affect the internal procedure of TPS65086470 but the pulling-down is a hard-force to shutdown the rails, is that correct?

    For example, I pulled-up CTL_1 but its switching from low/high or high/low to satisfy the power-up/down sequency will be handled internally, is that correct_?

    Based on this idea if you please check my configuration above while connecting the rails for Artix-7, in my design CTL_1, CTL_2,CTL_3 and CTL_6 are are pulled-up but CTL_4 and CTL_5 are pulled-down.  Could you please check my CTL connections?

    Besr regards,

    Ulas

     

  • 0 in reply to Ulas SAHIN
    TI__Mastermind 31840 points

    Hi Ulas, 

    Please see my comments on your questions below.

    Ulas SAHIN said:
    I see that only CTL1 and CTL2 have the control for Artix-7 configuration but I do not need to connect these pins to a control circuit since TPS65086470 already does the configuration job by itself. Is that correct?

    No this is not correct. Part of the preprogramming on the TPS65086470 is the assignment of CTL pins as the enable/disable for the output regulators. As you correctly identified in figure 8-15 CTL1 and CTL2 are the enable pins for all outputs besides VTT LDO. CTL1 and CTL2 need to be driven high (i.e. connected to a pull up supply) for the power up sequence to occur as described in the datasheet. 

    Alternatively, if you chose to not utilize the CTL pins all outputs can be enabled via I2C communication using the I2C_RAIL_EN1 and I2C_RAIL_EN2/GPOCTRL registers respectively. In this scenario the preprogrammed power up sequence would not be followed. 

    Ulas SAHIN said:
    What I understand is that the pulling-up of CTL pins does not affect the internal procedure of TPS65086470 but the pulling-down is a hard-force to shutdown the rails, is that correct?

    No this is not correct. For example, if input power is applied, but CTL1 and CTL2 = GND then no outputs will turn on. You are correct that pulling down CTL1 and CTL2 will force the power down sequence. 

    Ulas SAHIN said:
    For example, I pulled-up CTL_1 but its switching from low/high or high/low to satisfy the power-up/down sequency will be handled internally, is that correct_?

    No, the CTL pins are not pulled high or low internally. Any CTL pin that you do not plan to use should be connected to GND. 

    Ulas SAHIN said:
    Based on this idea if you please check my configuration

    CTL4 and CTL5 are not preprogrammed as the enable pin for any output you plan to use, so you are correct to connect these to GND.  For complete functionality I recommend having CTL1, CTL2, CTL3, and CTL6 connected to a control circuit where they can be driven either high or low.

    You are free to connect these pins to a pull up supply at all times, but you will then lose the ability to adjust BUCK6 and VTT LDO to their sleep mode voltage with CTL6, enable/disable VTT LDO with CTL3, and will need to control the power down sequence via I2C. 

    Let me know if you have any further questions. 

    Best Regards,

    Garrett 

  • 0 in reply to Garrett Kreger
    Prodigy 10 points

    Hi Garrett,

    Garrett Kreger said:
    As you correctly identified in figure 8-15 CTL1 and CTL2 are the enable pins for all outputs besides VTT LDO. CTL1 and CTL2 need to be driven high (i.e. connected to a pull up supply) for the power up sequence to occur as described in the datasheet. 

    What I try to understand is this. Lets say CTL1 and CTL2 are pulled-up to LDO3P3 at all times.  When I look at the Figure 8-15, CTL1 needs to go from low to high so that BUCK1 and BUCK2 will power-up. How will this low-to-high transition happen? It will be performed by TPS65086470? Similarly, during power-down CTL1 and CTL2 needs to high-to-low transition even if they are pulled-up at all times. How will that happen without a control circuitry? 

  • 0 in reply to Ulas SAHIN
    TI__Mastermind 31840 points

    Hi Ulas, 

    Let me attempt to clarify further. 

    The CTL pins are considered digital inputs. For the power up sequence to function CTL1 and CTL2 simply need to be driven high. A literal low to high transition is not required. If CTL1 is logic high following the connection of an input supply to Vsys BUCK1 and BUCK2 will power up. 

    You are correct that control circuity is needed to have the power down sequence follow figure 8-16. If CTL1 and CTL2 are always pulled high power down can only be controlled via I2C or when input power is removed. 

    Ulas SAHIN said:
    It will be performed by TPS65086470?

    All CTLx pins are inputs only. The TPS65086470 will never internally drive a low to high or high to low transition of these pins. 

    Best Regards,

    Garrett 

  • 0 in reply to Garrett Kreger
    Prodigy 10 points

    Hi Garrett,

    So you are saying that all-time pulling-high of CTL1 and CTL2 will not work since the power-down sequence requires high-to-low transition and it can be only done via I2C?

    All control pins can be configured via I2C to satisfy power-up and power-down sequence for TPS65086470 , is that right? Without using external control circuitry, it can be performed via I2C? If so, is there any document for the details of I2C control?

    Best regards,

    Ulas

  • 0 in reply to Ulas SAHIN
    TI__Mastermind 31840 points

    Hi Ulas, 

    Ulas SAHIN said:
    So you are saying that all-time pulling-high of CTL1 and CTL2 will not work since the power-down sequence requires high-to-low transition

    This is correct. The power down sequence requires CTL1 and CTL2 to be driven low to disable output rails. I2C writes from a host can also be used to disable each output rail. 

    Ulas SAHIN said:
    All control pins can be configured via I2C to satisfy power-up and power-down sequence for TPS65086470 , is that right?

    The control pins themselves (CTL1 through CTL6) cannot be reconfigured. The will only be able to function in the manner previously discussed in this thread. I2C communication is an alternative option to enable and disable the output regulators.

    If you chose to not use external control circuitry with the CTL pins then I2C write commands could be used to enable/disable each individual rail via  I2C_RAIL_EN1 and I2C_RAIL_EN2/GPOCTRL registers. Details on these I2C registers can be found on page 85 and 86 of the datasheet. 

    To summarize, driving the CTL pins either high or low is only way to trigger the power up and power down sequences as described in figures 8-15 and 8-16. I2C communication is an alternative method to enable/disable each BUCK and LDO output. 

    Best Regards,

    Garrett 

  • 0 in reply to Garrett Kreger
    Prodigy 10 points

    Hi Garrett,

    Thank yo so much for your help.

    I think we will go with the I2C control. While using I2C control, CTL_1 and CTL_2 will be always pulled-up on the PCB. This will not affect the power sequence control via I2C, is that right? 

  • 0 in reply to Ulas SAHIN
    TI__Intellectual 2101 points

    Howdy Ulas.

    Garrett will be available again next Tuesday to answer your question.

    Best,

    David Martinez

  • 0 in reply to David Martinez
    TI__Mastermind 31840 points

    Hi Ulas, 

    With CTL1 and CTL2 always pulled up the power up sequence defined in figure 8-15 will occur as soon as input power is provided to the PMIC. Then I2C will be required to control the power down sequence. If this works for your system then there is no problem having CTL1 and CTL2 always pulled up to logic high on the PCB. 

    Ulas SAHIN said:
    This will not affect the power sequence control via I2C, is that right?

    Correct, even with CTL1 and CTL2 always pulled up all output rails can be enabled and disabled via I2C. 

    Best Regards,

    Garrett 

  • 0 in reply to Garrett Kreger
    Prodigy 10 points

    Hi Garrett,

    I tried to design a configuration without considering the I2C control because it will not happen in our design because there is no possibility that we use something as a system controller.

    Could you please check the connections for manuel control of CTL1 and CTL2 during power-up? Also I kindly ask you to answer my questions at the attached document.

    Best regards,

    /resized-image/__size/320x240/__key/communityserver-discussions-components-files/196/power_5F00_solution.jpg

  • 0 in reply to Ulas SAHIN
    TI__Mastermind 31840 points

    Hi Ulas, 

    Please see my comments below. 

    1) There is no required delay between LDO5 and LDO3P3 turn on and the CTL1 transition to a high state. The diagram is showing that LDO5 and LDO3P3 will turn on after input to Vsys is provided, whereas BUCK1 and BUCK2 outputs require CTL1 = high to turn on. 

    Since there is no required delay I do not believe the TPS3808 is necessary. In your block diagram you are already using the LDO3P3 pin as the pullup supply for the RESET output. You can remove the TPS3808 and connect CTL1 directly to LDO3P3 pin. 

    2)Yes you can connect GPO1 to CTL2, although if you are now looking to initiate power down sequence via CTL pins this is not recommended because CTL2 needs to be driven low before GPO1 will transition low, as shown in figure 8-16. If you are still planning to use I2C for power down control there is no problem connecting GPO1 to CTL2. 

    Similar to the answer to number 1, there is no required delay between GPO1 and CTL2. CTL2 could be driven high before GPO1 transitions high and there would be no issue. 

    Regards,

    Garrett 

  • 0 in reply to Garrett Kreger
    Prodigy 10 points

    Hi Garrett,

    I think we have an agreement on connecting CTL1 to LDO3P3 via pull-up resistor and it will work fine during power-up, right?

    Garrett Kreger said:
    2)Yes you can connect GPO1 to CTL2, although if you are now looking to initiate power down sequence via CTL pins this is not recommended because CTL2 needs to be driven low before GPO1 will transition low, as shown in figure 8-16. If you are still planning to use I2C for power down control there is no problem connecting GPO1 to CTL2. 

    Please let me re-state that I will connect directly GPO1 and CTL2, they will be connected to LDO3P3 via pull-up resistor. This will not be a problem during the manual power-up (not using I2C control), right?

    The power-down will be a problem for us because I think TPS65086470 needs to have VSYS and the other external voltages during power-down and it is impossible for us because on system-level,for us,power-down will mean to remove all external voltages before putting TPS65086470 into power-down sequence. Thus, we will probably use TPS65086470 in emergency shutdown mode during power-down. Do you think it would be a problem for the device considering long-term use? We may harm the device by using it in emergency shutdown mode always during power-down? I would appreciate if you can suggest something that we can apply on system level so that we power-down the device when there is no external voltage source

    Best regards,

    Ulas.  

  • 0 in reply to Ulas SAHIN
    TI__Mastermind 31840 points

    Hi Ulas,

    Please see my comments below.  

    Ulas SAHIN said:
    I think we have an agreement on connecting CTL1 to LDO3P3 via pull-up resistor and it will work fine during power-up, right?

    Correct. 

    Ulas SAHIN said:
    I will connect directly GPO1 and CTL2, they will be connected to LDO3P3 via pull-up resistor. This will not be a problem during the manual power-up (not using I2C control), right?

    Correct, connecting GPO1 and CTL2 to LDO3P3 via pull-up resistor will work for power up. 

    Ulas SAHIN said:
    Do you think it would be a problem for the device considering long-term use? We may harm the device by using it in emergency shutdown mode always during power-down?

    Always turning the PMIC off via emergency shutdown is not a problem for the PMIC. There should not be long term use risk by doing this. Although, I recommend you check if always turning off via emergency shutdown is an issue for the processor. 

    Best Regards,

    Garrett