TPS546D24A: Short issue between SW and GND

David Park 

I see a number of issues with your schematic and layout design, though I'm not sure if they are directly related to your switch node failure or not.

1) AVIN should be filtered from PVIN by a 10μs filter, not directly connected to PVIN

2) The series boot resistor should not be more than 4.7Ω

3) Your use of ground symbols with AGND representing the main system / power ground, and the ground symbol for the local isolated analog ground is concerning about how the circuit is connected to the overall system

4) The AGND pin is no directly connected to the exposed PAD PGND, as required by the datasheet, but separated by an external resistor R27

5) You did not share the back-side component placements, but C28, one of the 6.8nF bypass capacitors is located on the far side of C26 and C30 where the trace inductance to the capacitors is preventing it from effectively providing high-frequency, low-inductance bypassing of PVIN to PGND

6) I can't locate C50 and R29 (Snubber) on your layout, nor do I see vias in the SW node to connect to C50 / R29 on the backside of the PCB.  Like the 6.8nF input capacitors, the snubber needs a very low inductance path back to the exposed thermal pad to be effective.

Based on the layout of C28 and the snubber components, I suspect that the root cause of the low-impedance from SW to PGND is MOSFET failure due to over-voltage stress from switch node ringing.

Do you have a board that is working where you can measure PVIN and SW with respect to the PGND pins, taking voltage measurements as close to the IC Pins as possible and with the only oscilloscope ground connection to the PGND pins on the end of the TPS546D24A IC?

5V per division, 20ns per division, no bandwidth limiting on the oscilloscopes.  trigger point 20% of the horizontal scale (2 of 10 divisions from the left most edge)   One image triggering on the rising edge, one triggering on the falling edge.  So we can look at the ringing on the switching node.

David,

I also see the multi-phase stacking connections for this design going off page, but I can't see the MSEL2 programming to know if this is a lead device in a multi-phase stack or not.  Is this part of a multi-phase stack or a stand-alone single phase application?