This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC2897A: UCC2897A_54V to 12V/21A design question

Part Number: UCC2897A
Other Parts Discussed in Thread: PMP9656

Hi TI partner,

Currently, I'm design ACF topology that using UCC2897A for Vin:43V~60V to Vout:12V/21A application, as below is my design questions list, need your help to clarify them.

Q1: refer to PMP9656, the transformer is "RA6992-BL", I want to use "PH0908.002NL" to replace it, need your help to double confirm its spec.

        RA6992-BL:  Pri-Sec-Aux=8T:4T:4T=> turn ration: 2:1:1; Pri-inductance=50uH  https://www.coilcraft.com/en-us/products/transformers/planar-transformers/planar/ra6992/

        PH0908.002NL:  Pri-Sec-Aux=4T:2T:2T=> turn ration: 2:1:1; Pri-inductance=>211uH/2/2=52.75uH (Pri-A parallel Pri-B) https://productfinder.pulseelectronics.com/part/ph0908nl   

Q2: refer to PMP9656, T2 should be for current sensing, what is the function of R3? Why it parallel with T2 ? As I know, it will separate the current path that flow to T2 & R3 that means T2 will not sense the total current            of  Q5 &Q6, so the reporting "CS" will be wrong? 

Q2-1: If I don't use T2 for current sensing, and I connect a R-sense and series with Q5/Q6 source pin for current sensing. Is it workable? The Cons/Pros is?

Q3: In MOSFET parallel application, we usually series R-Gate in each MOSFET to ensure consistent on/off timing, but in PMP9656 sch, I only see one R-Gate/R100 for Q5/Q6? Why?

Q3-1: R100 place location, seems to make lower turn-on speed and faster turn-off speed, am I right? If not, please correct me.

Q3-2: SR FET: Q1/Q2 and Q4/Q7 not seen R-Gate for each FET, is it need to reserve to ensure the consistent on/off timing of parallel MOSFET? 

Q4: regarding to EMI testing, since our system need to pass Class-B, is there any solution need to reserve in advance or special layout guideline for this? Please recommend, thanks!

Looking forward your reply!

  • Simon,

    Q1: refer to PMP9656, the transformer is "RA6992-BL", I want to use "PH0908.002NL" to replace it, need your help to double confirm its spec.

            RA6992-BL:  Pri-Sec-Aux=8T:4T:4T=> turn ration: 2:1:1; Pri-inductance=50uH  https://www.coilcraft.com/en-us/products/transformers/planar-transformers/planar/ra6992/

            PH0908.002NL:  Pri-Sec-Aux=4T:2T:2T=> turn ration: 2:1:1; Pri-inductance=>211uH/2/2=52.75uH (Pri-A parallel Pri-B) https://productfinder.pulseelectronics.com/part/ph0908nl

    • ok, one thing to watch for is the delay time from primary to secondary may be different when you switch transformers. Since the design uses self driven SR technique, there could be a timing difference encountered when comparing the two transformers - something to be aware of and test for.

    Q2: refer to PMP9656, T2 should be for current sensing, what is the function of R3? Why it parallel with T2 ? As I know, it will separate the current path that flow to T2 & R3 that means T2 will not sense the total current            of  Q5 &Q6, so the reporting "CS" will be wrong? 

    • R3=100 mΩ and is in parallel with T2:7-8 which is 0.7 mΩ. Most of the current will flow through the 0.7 mΩ. R3 could be for the purpose of filtering or dampening ringing seen on the CS signal.

    Q2-1: If I don't use T2 for current sensing, and I connect a R-sense and series with Q5/Q6 source pin for current sensing. Is it workable? The Cons/Pros is?

    • Yes, this would serve the same purpose and result in the same waveform as long as the CS resistor is sized correctly and can handle the power dissipation.

    Q3: In MOSFET parallel application, we usually series R-Gate in each MOSFET to ensure consistent on/off timing, but in PMP9656 sch, I only see one R-Gate/R100 for Q5/Q6? Why?

    • There is no rule for where this gate resistor must be placed. If I were starting a new design, I would do as you mentioned and place a single resistor at the gate of each MOSFET.

    Q3-1: R100 place location, seems to make lower turn-on speed and faster turn-off speed, am I right? If not, please correct me.

    • I don't see R100 on the schematic?

    Q3-2: SR FET: Q1/Q2 and Q4/Q7 not seen R-Gate for each FET, is it need to reserve to ensure the consistent on/off timing of parallel MOSFET? 

    • Probably won't help much with SR timing adjustment and in my experience with this application, I've not needed gate resistors on SRs. If you want to add placeholders just in case, go ahead.

    Q4: regarding to EMI testing, since our system need to pass Class-B, is there any solution need to reserve in advance or special layout guideline for this?

    • Active clamp forward is using ZVS so should give good EMI performance. I've not tested UCC2897A for EMI so maybe make sure to add placeholders for CM and DM line filter as well as primary-to-secondary Y-capacitor.

    Regards,

    Steve M

  • Hi Steven,

    Thanks for your quickly reply! some question need discuss with you.

    Q1: Regarding to the delay time from primary to secondary, I don't see the spec on datasheet. What parameter of transformer would cause the difference?

    eg. parasitic capacitor between Pri and Sec, air gap....or something else.

    Q3-1: see below picture for R100 location. This location will reduce the turn on speed, but won't slow down turn-off speed, right? Is there any design tip for this circuit that I need to follow it?

    Q4: Yes, I reserve Y-cap, 1000pF/3KV_PC276 between Pri-to-Sec and snubber for SR and Pri-FET, please see below. Could you share the CM/DM design application note to me for reference, thanks!

  • Q1: Regarding to the delay time from primary to secondary, I don't see the spec on datasheet. What parameter of transformer would cause the difference?

    • Primary to secondary delay time is not something a transformer vendor will specify but there is an associated delay time and I just wanted to make you aware that if your change transformers and the the utrns/constructions is different, the delay time may be different. In most cases this difference is negligible but when using self-driven SR, it may matter.

    Q3-1: see below picture for R100 location. This location will reduce the turn on speed, but won't slow down turn-off speed, right? Is there any design tip for this circuit that I need to follow it?

    • A gate resistor used in the location shown will reduce turn-on dv/dt and turn-off dv/dt. We last discussed adding a dedicated gate resistor to Q5 and Q6 and if you want to control the turn-on and still have fast turn-off, you need to do something like below and also I recommend you read SLUA618A which is considered the goto guideline/App Note for gate drive circuits.

    Q4: Yes, I reserve Y-cap, 1000pF/3KV_PC276 between Pri-to-Sec and snubber for SR and Pri-FET, please see below. Could you share the CM/DM design application note to me for reference, thanks!

    • I don't have an app note for CM/DM filter design but many sources can be found by searching "EMI Filter Design" at TI.com.

    Regards,

    Steve M

  • Hi Steve,

    Thanks for your clear feedback!ThumbsupThumbsup