TPS6594-Q1: FuSa questions about TPS6594133A+TPS389006-Q1 for J784S4 PDN-3A

Hello Shubiao,

The two TPS389006x monitors should be connected as below:

The MAIN_PWRGRP_IRQn signal should be connected to PMIC's GPIO8 and MCU_PWRGRP_IRQn should be connected GPIO10.

After the system boots, SW must unmask the interrupts on GPIO8 and GPIO10 in order for the PMIC to react to signals from voltage monitors.

If GPIO Retention low power mode is desired, then connect all the SVS-B VMON inputs to existing MCU supplies (as shown) sorced from the PMIC to avoid any false positives on unconnected voltage monitor signals.

-Mike

hi michael,

Thanks for your help.

The question is

1. The logic related to reaction of PMIC after SVS-A/B report error by IRQn, we can't find any description about them.

2. Based on the usecase with ASIL D, these error report path shall be tested by BIST or other way, we can'f find them either.

So please help give some info about these logic.

BR

xiaowei

Hello Xiaowei,

After PMIC's GPIO8 and GPIO10 interrupts are unmasked the PMIC will react in these ways:

On falling edge of MCU_PWR_GRP_IRQn ( connected to GPIO10), the PMIC will execute an Orderly Shutdown of all the rails.

On falling edge of MAIN_PWRGRP_IRQn ( connected to GPIO8), the PMIC will shut down the rails which power the SOC, but leave the rails associated with powering the MCU enabled.

I need to get back to you with answer to your second question.

Regards,

Mike

hi Michael,

Thanks for your reply.

In my view, these functions(IRQs monitored by PMIC) are related to safety, and shall be added in functional safety manual and FMEDA, but we can't get any info from TI's offical document, and these functions shall be related to PMIC's NVM. So can we get that info from any offical documents?

BR

xiaowei

The User Guide for the TPS6594133A is in final stages of being officially published. It will include specific details of this PMIC NVM and GPIO connections for functional safety.

-Mike

hi Michael,

Thanks for your reply.

May i ask when will the userguide be officially published?

And in TPS6594 safety manual(SLVUBP7A-APRIL 2021), the following SA is not applicable for TPS6594133? 

Are there any other deviations between 4133 application and TPS6594 safety manual(SLVUBP7A-APRIL 2021)？

BR

xiaowei

Hi,

Sorry for the delay. Please expect a response tomorrow.

Best,

David Martinez

hi mike,

Thanks for your reply.

May i confirm that the discrete voltage monitors (TPS389006x) is ASIL B or ASIL D?

Yes, I agreed your comments 'there aren't any other deviations', but from PMIC(TPS6594133A)'s application, the following SA can not be satified(we can't get this info about functions(IRQs monitored by PMIC) from safetymanual/FMEDA, in userguide doc, there is not function description, IRQ is mentioned only).

BR

xiaowei

The discrete voltage monitors help give the system achieve ASIL B by enabling the monitoring all rails in the PDN.

However, if a power system is design with other means of monitoring rails the PMIC doesn't provide that would be an option as well. For example, in a system with TPS6594133A and only 1 other discrete power component supplying a critical rail, the PGOOD of that supply could feed into GPIO8 or GPIO10 instead of adding an additional monitor.

hi mike,

Thanks for your help.

From datasheet, TPS38906 has ASIL D capability, Can you please help to confirm 'it is ASIL B/ASIL D'?

BTW, can we get some info about GPIO8/GPIO10 functional description from PIMC offical documents?

BR

xiaowei

For J7 applications, OV/UV monitoring is needed for ASIL B. The TPS389006 provides this monitoring for rails the PMIC doesn't power/provide in the system.

I will provide GPIO8/10 by COB.

hi mike,

Thanks for your reply.

-From the lastest PDN, there are power supplys for MCU domain are monitored by TPS389006, is it ASIL B?

-COB is 'Change of ?'

BR

xiaowei

Howdy Duan,

Sorry for the delay. Please expect a response tomorrow.

Best,

David Martinez

GPIO8 is configured as a digital input with the internal 400kohm pulldown enabled. The logic level is latched before 3ms time step during the power up sequence & directs the PMIC to configure internal resources as follows:

• Low = PMIC creates 2x power groups (MCU and SOC/MAIN); Enables BUCK5 per power up seq
• High = PMIC creates 1x power group (recognized by PMIC as MCU); Removes BUCK5 from power up seq (Allow system SW to reassign Buck5 for supplying peripheral devices that can be enabled after boot)

For PDNs with split power groups, GPIO8 is expecting an active low interrupt signal from the voltage monitor on the MAIN/SOC power group rails not powered by the PMIC. If GPIO8 goes LOW, the PMIC reacts as if SOC_PWR_ERROR has occurred. To achieve this, connect to GPIO8 like below with a 3.3V level translator from VDA_DLL_0V8 (PMIC LDO3) and the open drain interrupt output of the MAIN_PWRGRP voltage monitor.

GPIO10 is configured as a digital input with the internal 400kohm pulldown enabled. After power up it is expecting an active low interrupt signal from the voltage monitor on the MCU power group rails not powered by the PMIC. If GPIO10 goes low, the PMIC reacts as if an MCU_PWR_ERROR has occurred and executes an ORDERLY_SHUTDOWN.

For PDNs using a single power group, tie GPIO8 HIGH to VCCA_3V3. Combine the open drain interrupt outputs of both voltage monitors into a single signal MCU_PWRGRP_IRQn and connect that signal to GPIO10.

hi michael,

Thanks for your detailed reply and now we get the function of GPIO8 and GPIO10 of TPS6594, may i ask the process of following questions?

BR

xiaowei

Hello,

Thank you for reaching out. The device expert is out of office due to holiday in US. Please expect delay in the response by tomorrow. 

Thank you in advance for your patience!

Best regards,

David Martinez

xw Duan said:

-From the lastest PDN, there are power supplys for MCU domain are monitored by TPS389006, is it ASIL B?

The latest PDN diagrams show the connections necessary for ASIL D.

xw Duan said:

-COB is 'Change of ?

COB stands for "Close of Business". I apologize, it is an English language figure a speech referring to time.

-Mike

hi mike,

Thanks for your reply.

1.In previous reply, you said the discrete voltage monitors help give the system achieve ASIL B? not ASIL D

Michael Gambrill said:

The discrete voltage monitors help give the system achieve ASIL B by enabling the monitoring all rails in the PDN.

2. May i ask is there any process about this user guide? 

Michael Gambrill said:

I am pushing to have the user guide officially published by February 13th.

BR

xiaowei

ASIL-D is above ASIL-B. To achieve ASIL-D, as system needs to at least be ASIL-B. The voltage monitors are required for ASIL-B, therefore they are also required for ASIL-D.

We had some last minute feed back from our tech writers and the user guide should go up shortly.

hi mike,

Thanks for your reply.

I still have doubts about the rationality of ASIL D requirements.

We suppose that the voltage monitor is allocated as ASIL D because of it monitors ASIL D domain(MCU domain) power supply, please help to confirm.

BR

xiaowei

xw Duan said:

We suppose that the voltage monitor is allocated as ASIL D because of it monitors ASIL D domain(MCU domain) power supply, please help to confirm.

I have requested additional confirmation from our safety expert on the matter.

hi mike,

Thanks for your reply.

Could you please explain this concept? Why ASIL B can satisfied ASIL D concept?

Michael Gambrill said:

We suppose that the voltage monitor is allocated as ASIL D because of it monitors ASIL D domain(MCU domain) power supply, please help to confirm

BR

xiaowei

ASIL-D is a higher safety grade than ASIL-B.

ASIL-B requires OVUV voltage monitoring, but not Over Current Protection like ASIL-D. Table 3-2 from the user guide highlights the power monitoring features for ASIL-B and additional monitoring needed for ASIL-D.

Regards,

Mike

hi mike,

Thanks for your reply.

Can i understand that TPS389006 has ASIL D OV/UV/Sequence monitor ability, but consider this use case, TPS389006 just provides ASIL B monitor because of no overcurrent monitor?

BR

xiaowei

Hello Xiaowei,

For our system overcurrent monitoring/protection is needed for ASIL-D.

If only ASIL-B is needed, then discrete LDOs without OCP can be substituted for LDOs A, B, C, and D in the system. 

hi mike

Thanks for your reply.

I can't following you and  still have doubts about it. Let's put it another way

Voltage Monitors are required for ASIL D because of it is responsible for monitoring power rail of MCU domain(ASIL D). I cannot understand the following description.

Michael Gambrill said:

Regarding the voltage monitors, they are required for ASIL-B. However if GPIO and DDR Retention low power modes, several of the discrete power resources along with 1 voltage monitor can be removed. Further details are provided in user guide.

BR

xiaowei

Howdy Duan,

Sorry for the delay. Please expect a response from Michael by tomorrow.

Best,

David Martinez

Hello Xiaowei,

Other options to consider for downgrading from an ASIL-D safety-concept to an ASIL-B:

• using less accurate voltage monitors
• using voltage monitors that don't have ABIST/LBIST
• decide (based on failure in time rate of the discrete power resources) to not monitor each discrete regulator, but only the ones that have the higher FIT rate.

-Mike

hi Mike,

Thanks for your reply.

The last question is that the following differences need to be clarified:

-You said "Regarding the voltage monitors, they are required for ASIL-B."

-From my view "Voltage Monitors are required for ASIL D because of it is responsible for monitoring power rail of MCU domain(ASIL D)"

So why ASIL B monitor can meet the safety concept of ASIL D(related to MCU domain)?

BR

xiaowei

hi Phil,

Very thanks for your reply, and I understand this concept now.

More questions, could you please provide some advice that "which mechanisms can be added by the host that can satisfy full asil d"?

BR

xiaowei

Xiaowei,

Even with monitoring features in PDN-3A, there are still software requirements on the processor for error handling and communicating with the watch dog.

-Mike