Hi Team,
Tps22918 is discussed as an application of FPGA power supply sequences.
This time, the power good signal of the other power supply IC (the power supply rise completion signal) is input to the ON pin of TPS22918 to start the power supply sequentially.
The power good signal output of the power supply IC to be used is an open drain.
When the power supply IC power up, a delay occur on the power good signal since capacitor and pull-up resistor are connected on the circuit of the power good signal.
For example, do you have any limit of rise time(to 1 V of H level) of the input signal to the ON pin of TPS22918?
In the case of a signal with a long rise time, for example, is there a possibility of an operational problem such as repeat of ON・OFF on the Vout of TPS22918?
Best Regards,
Tom
