Good morning sirs,
I have some doubts regarding to watchdog tolerance. I will show it with an example:
Let's suppose this configured values.
WD_WIN1_CFG = 0x7F (127)
WD_WIN2_CFG = 0x1F (31)
tWIN1_MIN = [(RT[6:0] – 1) × 0.55 × 0.95] ms = 65.835ms
tWIN1_MAX = (RT [6:0] × 0.55 × 1.05) ms = 73.3425ms
tWIN2_MIN = [(RW[4:0] + 1) × 0.55 × 0.95] ms = 16.72ms
tWIN2_MAX = [(RW[4:0] + 1) × 0.55 × 1.05] ms = 18.48ms
That would mean that in case of having a periodical signal of 10ms, in order to ensure answering in windows 2 we have to answer in time 80ms?
( >73.3425ms and <73.3425ms + 16.72ms) and ( < (65.835ms +16.72ms = 82.5ms) ) But avoiding to delay the answer more than 82.5ms or we would risk to trigger timeout at watchdog, depending if that time was a minimal size window or max size window.
So the watchdog has a big deviation in which window 1 can change to windows 2 , in the worst case, with a difference of 8ms. Isn't it a big indetermination for window time?
If we configured a smaller value for win2, for example RW[4:0]=15 tWIN2_MIN = 8,36ms tWIN2_MAX = 9,34ms , it would be very probable to fall out of the window time due this previous indetermination.
I am reading something wrong? Is strange for me.
There is any way via SPI registers or DIAG_MUX to know if we are in window 1 or window2 in order to detect the transition and improve timing synchronization?
