BQ77915: External Cell Balancing Schematic Review

Hello Muki,

The circuit is implemented incorrectly, the drain/source for each N-FET should be flipped, similar to the following figure:

Also yes, I would recommend you add Zener diodes on the gate-source of the FET. This is to protect the FETs in event of large transients where the gate-source voltage could potentially exceed its absolute max values.

This figure is from an application note for a different device family (The BQ769x2 family), however the cell balancing concepts still apply for this device. Here is the app note:

• Cell Balancing With BQ769x2 Battery Monitors

Why are you using external cell balancing? You have a 10-kOhm for the balancing resistor, this seems to be a very large resistor value, a 4.2-V cell would have a balancing current of just 0.42-mA through this resistor, making it almost useless. Most of the balancing in this case would be due to the internal cell balancing FET, which would be at its worse 4.2V/(1000+1000+20) = 2-mA through the internal balancing FET. 

Using the internal FETs and an input resistance of 33-Ohm, you can achieve up-to 50-mA of balancing current without the use of external FETs. If a larger balancing current is desired, then you would need to use the external cell balancing circuit.

I also just noticed that you mention that you are using LFP cells for your system, these tend to have a lower overall, so make sure to select a device that is able to support your desired protections. Also cell balancing will only start above a certain voltage (V_START), see the device comparison table to see if any fit your cell chemistry.

To talk a bit about the rest of your circuit:

• I would recommend to use a net-tie or 0-Ohm resistor to connect BAT- and the BQ77915's ground (Vss), this is to keep the batterie's high current path separate from the IC component. 
  • This also helps with ESD ruggedness.
  • Add ESD capacitors across the DSG/CHG FETs.
  • See the EVM schematic for some guidance in this: https://www.ti.com/tool/BQ77915EVM-014 
• The CHG FET is incorrectly placed, the source of the CHG FETs (Q3 and Q4) should connect to PACK-.
  • You should look at and consider the CHG FET sections of the datasheet (Section 10.1.1.2 Protecting CHG and LD and Section 10.1.1.3 Protecting the CHG FET)
    • This is very important and at the very least would recommend to add a 16-V Zener across the gate-source of the CHG FET.
• You should have filtering components for your sense resistor. This is greatly recommend (See Section 10.1.1.6 Adding RC Filters to the Sense Resistor of the datasheet).
  • This is also seen in the EVM and our application notes.
• I also would recommend you read the Multiple FETs app note for the BQ77905, which is the previous iteration of this device, but the same concepts still apply for this.

These are some of the things I noticed on this. Please let me know if there are any more questions .

Best Regards,

Luis Hernandez Salomon

Hello Muki,

1. corrected the source direction for Balance FETs
Looks good.

2. added zener diodes to gate-source of the balance FETs
Looks good.

3. replaced the 10-kOhm balance resistor with 20-Ohm resistor. Vstart for BQ7791506 is 3.5V - At 3.6V, the balancing current will be 180mA + the internal balance current of 3.6V / (100+100+20) = 16mA. so, the total balancing current is roughly 200mA.
This seems reasonable. With 100-Ohm resistors you will have a gate-source voltage of roughly 100*0.016 = 1.6-V, so you just have to ensure that you FET can be turned on at this stage. Something else to consider is the MOSFET capabilities at these voltages. Is the RDSON acceptable at a 1.6-V level?

4. source of CHG FET Q3 and Q4 is corrected
Looks good.

5. added 16V zener diode across gate source of CHG FET
Looks good.

6. added filter components for sense resistors as per 10.1.1.6 as per datasheet
Looks good.

7. added protection for CHG pin and LD pin as per 10.1.1.2 and 10.1.1.3
The D7 diode is backwards, this should be flipped. The purpose of the diode is to provide a fast turn-on. R11 should be a 1-MOhm resistor, which is used to limit the current into the pin. You should have an additional resistor before D7 and after Q9 (Like the 1-kOhm you initially had), in order to control the switching speed of the MOSFET. 

8. added ESD capacitors across CHG/DSG FET as per BQ77915EVM-014
Looks good.

9. used 0-Ohm resistor between VSS and BAT-
Looks good. The EVM is a good starting point to see a high current path for the battery current.

a. can you pls check if the ESD capacitors are added correctly (new to the concept)
Yes this seems okay to me. You may want to add ESD Caps between PACK+/PACK-. Here is an application note that explains some of the ESD concepts, which will be useful for you:  SLUA368. This is for a gauge, but the same concept still applies.

b. should i add diodes in parallel with the CHG and DSG FETs ? 
You do not need to add diodes in parallel to the CHG/DSG FETs.

c. should i use 0-Ohm resistors to connect CTRD and CTRC to ground ?
This is not needed. In the EVM these are placed because because we sometimes do not want to connect these to ground (when we are stacking them for example)

Best Regards,

Luis Hernandez Salomon

Hello Muki,

I've fixed this mistake. Changed the direction of the D7 diode and increased the value of the resistance to 1 M-Ohm. Also added a 1-kOhm resistor between the CHG pin and Q9 MOSFET
I would only have the R26 resistor after Q9 and before D7/R11. Else this all looks really good.

I've changed the resistor value to 1k-Ohm as recommended in 9.3.4 in SLUSCU0J. Also, I've chosen a MOSFET with Vgs(th) of 1.05V to 1.45V and Rds(on) of 50-mOhm at Vgs = 2.5V. I'm guessing this should work fine as it is recommended to select a MOSFET with threshold voltage less than 1.7V in SLUSCU0J. 
It may be okay, you will have ~1.78-V drop across the gate-source when using 1-kOhm resistors (You are correct this is the best value for external cell balancing). Do remember that the Rdson will change exponentially the closer it is to turn-on voltage. If you have any on-hand it may be good to to measure what is the resistance at ~1.78-V.

i wanted to add TVS diodes in parallel but since the ESD capacitors that you recommended will take care of surges, i'm going to leave it as is
That sounds good. I've seen some customers add TVS diodes across PACK+/PACK- before if needed. But the ESD caps themselves should be okay.

a. if i'm looking to use the OCD functionality, are there any reference designs i could look into for learning ?
Section 10.2.2.1 Design Example of the datasheet is a good point to start to select an appropriate sense resistor for the OCD function.

b. what is the maximum balancing current recommended in case of external balancing , so that i could use the BMS with higher capacity battery packs ? (100Ah and higher)
The maximum balancing current at the end would become dependent on what FET you use, how much current it is able to handle and its thermals. If handling a lot of current, they could become pretty hot, so this should be taken into account. You may also have to use multiple external balancing resistors in parallel in order to handle higher currents. At 20-Ohms (Ignoring MOSFET resistance) your current external balancing resistor should be able to handle 3.6-V*0.18-A = 2 Watts of power. So that would be something else to take into account.

Of course! Let me know if you have any other questions that I can answer.

Best Regards,

Luis Hernandez Salomon