TPS59650: Can TPS59650 be used an alternative of TPS59641?

Edited: TPS59641 is used in Evaluation board by Bakersport. 

Hi Raj, 

Can you send the E2E post that said the TPS5950 cannot be used as an alternative to the TPS59641?
It should be okay. Both of the boot voltages are similar.

The difference in the devices is that the TPS5950 is able to handle two phases of GPU output instead of one. 

Best,

Ryan

Hello Ryan, 

Thanks for the response. 

Please click on the link to view the post that says TPS59650 cannot be used as an alternative of TPS59641. 

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1069214/tps59641-alternative-of-tps59641rslr

Also, Please help me out with understanding what exactly Boot Voltage is? and how does is matter?

Thank You 

Raj Kumar

Hi Raj,

This post is saying that the boot voltages for the parts are not the same. The customer wanted a part that was IMVP7 compatible and have a VBoot of 1.1 V. The TPS5960 looks to have a Vboot of 2 V and is IMVP7 compatible. 

Boot voltage is the voltage used to make sure when the switching is low, there is charge being stored in the capacitor. Vin > Vboot so there will current that flows from diode. 
When SW is high, Vin < Vboot and no current flows from the diode. Vboot is placed as the gate voltage of the high side N-mosfet so that there is a voltage between gate and source so it can turn on the mosfet. 

Best,
Ryan

Hello Ryan, 

Thank you for the explanation, I got the point. 

I want to add one more concern here.

I tried so many times to simulate the design with TPS59650 using Pspice & TINA-TI. But It shows error all the time. I received that Pspice model from TI support for TPS51650.

Without simulations, To make sure, the design doesn't have any small or major mistakes. You are requested to Please REVIEW the schematic. You may also try to simulate on yours end if possible. 

For the reference, please find attached schematic pdf. 

3051.SCHEMATIC1 _ PAGE1.pdf

My operating conditions are- 

Vin = 5V

VCC (CPU Phase 1) - 1V @ 4A.

VNN (GPU Phase 1) - 1V @ 10A

Thank You 

Raj Kumar

Hi Raj, 

Can you try this for your simulation issues?

(+) PSPICE-FOR-TI: An error has occurred within PSpice - Power management forum - Power management - TI E2E support forums

I looked at the schematic. It looks good to me. 

Best,
Ryan

Hi Ryan, 

Yes, My team has tried this technique also. Now it is not showing any error. but output waveform are not at all correct. please view attached output waveform once - 

I have one more thing to confirm. As I want 1V (VCC) & 1V (VNN) output supplies (default conditions). How this 1V (default case) is being decided. means at initial state of powering on (before SVID communication), this voltage to be generated?

Thank You

Raj Kumar

Hi

Team will look into the model.

As for your second question, please refer the functional overview of the data sheet. You can also refer the TPS59650 EVM user guide to see how the output works.

Regards

Yihe

Hi Rajkumar,

Can you please provide your PSPICE files. 

Hello Vasav, 

Yes, I have attached the ZIP file of PSPICE which I got from TI Support only. 

6470.TPS59650_PSPICE_TRANS.zip

I have one more thing to ask please help me out. 

While verifying the schematic using TI design spreadsheet named "TPS51650 Calculator DCR Sense_10kNTC QC", I noticed the OVERSHOOT REDUCTION field, in which there are 8 levels and OFF state. 

Please advice me which level should I use? (Note: I want to keep Overshoot and undershoot reduction Enabled).

Please find related snaps for the reference - 

Thank You 

Raj Kumar

Hi Rajkumar,

I will get back to you tomorrow.

Regards

Vasav 

Hi Raj Kumar,

Related to OSR: By default one can disable it. However, based on transient overshoot we tune this parameter. 

Related to PSPICE file, I have a quick questions.

1. The schematic has 3 power stages, but gate-driver circuit is placed with only one stage. Is there any specific reason for this, or I am missing something.

2. Only PWM3 is used, but PWM1 and PWM2 are unused. Are we not driving the other power stages?

3. Can you please share the link from where you got this file. 

Regards

Vasav 

Hello Vasav,

Please suggest which level should I consider for my operating requirement. (as I want to enable the OSR)

1. I need only two phases (one from CPU and one from GPU) and, CPU1 has its own internal gate-driver. 

2. Yes, I wanted to use only 1 phase of GPU (i.e. GPU1) for which GPWM1 was needed. 

3. Yes, please find the attached link for the same- 

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1200849/tps59650-simulation-model-for-part-no--tps59650/4529091#4529091

Please refer attached snap of TPS59650 simplifies block diagram for the reference - 

Thank You 

Raj Kumar

Thanks Raj Kumar for the information. 

I am working on the PSPICE and will get back to you by end of the week. I need to modify it to meet the application. 

For OSR point : This is application specific. OSR algorithm is a non-linear algorithm and we get its value by experiments only. In the beginning we make its value  "Disable" or "Maximum".  The maximum value in this case is Level 8 (610 mV)

Regards

Vasav