TPS3840: Datasheet block diagram may be incorrect

Andrew-san,

The logic state relation between VDD and /RESET is correct but, the logic state at CT is opposite.

It should be Low when VDD is higher than threshold and, it should be High when VDD is lower than threshold.

Is it correct?

Regards,

Hi Atsushsi-san,

For timing diagram purposes, there is no "logic state" for CT. It's merely used as a delay mechanism, and this delay is caused by charging/discharging the external capacitor.

Thanks,

Andrew

Andrew-san,

I know it.

High state means Pch FET is on and, CT charge current flows through Rct(internally it’s not a resistor but constant current source I think).

It should be happened when VDD is higher than the threshold but, in the diagram, it’s happening when VDD is lower than the threshold.

Regerds,

Hi Atsushi-san,

That TRC config is a CMOS inverter to a buffer going into another Cmos or Nmos inverter(depending push-pull or open drain). So yeah 11= 1 and everything else gives you 0. AND-gate logic works here.

Thanks,

Andrew

Andrew-san,

11 = 1 means "Not manual reset" AND "VDD is higher than the threshold" = High at the AND-logic.

When the AND logic output is high, Nch(low side) FET is ON and discharge the CT capacitor.

However, the CT capacitor should be "charged" when VDD is higher than the threshold.

If it's NAND, 11=0 and everything else gives you 1.

11 = 0 means "Not manual reset" AND "VDD is higher than the threshold" = Low at the NAND-logic.

When the NAND logic output is low, Pch(high side) FET is ON and charge the CT capacitor. It's as expected.

If my understanding is incorrect, could you draw a diagram to explain your story?

Regards,