Hello,
We have a network of TPS929240 chips integrated in our project.
It was observed that some chips do not respond to master readback requests.
Please note that the readback frames are transmitted to 2 chips consecutively every 40ms
For example, first cycle MCU reads from Chips#1 and #2, 40ms later MCU reads from Chips#3 and #4
After further investigation, it was observed that the second chip in each cycle was not responding.
However when frame scheduling is changed to read from a single chip every 40ms, with same master frame, all chips would respond normally
Also, when an extra delay is inserter between the read frames, all chips responded normally
When inter-frame delay is ~16us, second chip does not respond.
When it was increased to ~4300us, all chips responded.
Is there a specific inter-frame delay needed for communicating with the chips?
Please note that when reading the DBWTIMER register is returned a timer value of 250us
You may refer to the attached captures for your reference.
