UCC28781: Does not start up

I have made a mistake by using IPD80R600P7ATMA1 as Q2 which is supposed to be a depletion mode mosfet. I will place the original Q2 CPC3982TTR tomorrow and update this thread with my findings.

Dear Ulrich,

Thank you so much for your help.

Our output voltage will be 68V in the end design, i am glad you spotted the winding ratio being different so of course i will need to increase from 15V to much higher for this test board. I will also account for TLV having a different reference voltage.

Since the inductance in alternative transformer is higher, i calculated that i will need Rcs of around 0.9R to start up at 50V. Will do the change and see how it goes.

Below is the transformer design thats coming to us next week. Do you think there will be issues with using it as with the configuration provided in its datasheet? Of course converter components will have to be adjusted.

I double checked both TLVs and they both have 2.5V reference, even placed mine over the EVM and the EVM still outputs 15V.

I have placed in the original depletion nmos at Q3. Removed Q4. Placed around 2R Rcs, set Vout at around 31V. Tried input voltage up to 120V, output does not become active. Gate is always 0V, Vcs is 0V.

Vin during below measurements is around 32V.
Yellow is Q3 drain. 200mV/div. 200ms/div.
Orange is Q3 source. Red is Q3 gate. 2V/div. 100ms/div.
 

Below yellow is Vref. 2V/div. 100ms/div.                      VDD:

Do the graphs make sense?

I am looking into equations for RDM, RTZ, Rvs1 & Rvs2, are they essential right away or can i use EVM values for now? I just want to get started somewhere before i start changing too many values.

What else can i measure to debug this?

EDIT: I can see that my RUN and FLT pins are low, trying to find out why.

How come i calculate 190k for EVM Rrdm value while your EVM uses 93k?

Hello Valentinas, 

Thank you for the additional information.  It is going to take me a little while to analyze it all and provide some meaningful guidance.

But let me address your last question first.  I agree with your RDM calculation and you do have a good question.  At this moment, I don't know why the EVM uses ~1/2 the value that the calculation recommends.   Following up on some development history, the UCC28781EVM-053 design was mostly copied from a previous PMP22322 reference design which in turn was modified from an earlier PMP21552 design.  I think several changes were made along the way involving Lm, Npa, and Rvs1&2, but RDM was apparently not updated as these parameters changed.  Interestingly, the EVM still works so the PWMH control (which drives the SR for ZVS) is able to compensate for the under-value of RDM.  I'll have to investigate this situation some time when I get a chance.  

In your prior post, the REF and VDD waveforms make sense, but the two above them with 3 traces do not make sense to me.  They look like composites of three different sweeps pasted on top of each other.  The red and orange are vaguely similar but not coincident.  Still, some things may be gleaned from this. 
You say you placed a depletion-FET at Q3, but Q3 is the SR Fet.  I assume you meant Q2.   
In your EDIT, you report that RUN and FLT are low.  If they are always low and never pulse high even briefly, then there is a fault that prevents switching from starting.  The RED trace, which is Q2 gate which is HVG seems to drop from the peak of ~17V to 11V almost instantly may be the culprit.  

During the initial part of start-up, P13 tracks VDD closely.  At the turn-on threshold (near 17V), P13 is shifted to become a regulated 13V source and its voltage is normally bled down to 13V with a small current.  If there is an open on P13, it will drop to <14V very fast. 
Table 3 (DS page 53) indicates an open-P13 fault that prevents switching and cycles VDD through UVLO, which is what appears to be happening. 
Please check the connection of P13 at the controller and to the FET. 

As I mentioned, I'll need some time to digest the transformer information. 

Regards,
Ulrich

Hi Ulrich,

I did indeed talked about Q2 depletion-FET.

I have measured P13 on EVM, it looks exactly the same before Vin reaches 100V. Also measured the P13 fall time with Vin 30V, i see the same fall time on EVM and my board, which is 1ms and not faster than 10us so fault should not trigger.

On EVM, at Vin 32V, the RUN signal is low. How come at 100V the EVM knows that its time to start? I do not see any pins whose value varies with the Vin, they all seem to be fixed or zig-zagging.. Does it internally know? I am very confused on how to troubleshoot this.

EVM gate at Vin 32V is always low, how does it know that the Vin is 100V? How does it know when to start?

EVM FLT pin measurements: orange shoot happens every 1.6s or so, it is at Vin 32V, 200mV/div, red is at Vin 100V, 1V/div. 

Hello Valentinas, 

Okay, it's good to know that the fall time of P13 is much slower than 10us, so you're right, that will not trigger a fault. 

But something is triggering a fault, so we'll have to look further to find it. 
In the datasheet, Table 7-3 and Table 7-4 are lists of faults that result in shutdowns under various conditions.
You report seeing no gate drive, so that narrows down the possible faults to those that can occur before any switching happens.  

But first, let's verify two things: a) there is absolutely no gate drive pulse (no PWML) when VDD reaches the 17-V turn-on threshold, and b) there is no RUN signal when VDD reaches 17V.   You have to trigger on these signals with sweep speed of 2us/div to see them.  At 100ms/div, they may not be visible and you may think they are not there.  If they ARE there, you have to look at a different set of possible faults. 

Assuming RUN and PWML are not present, then from Table 7-3 it could only possibly be OTP fault on the FLT pin.  If FLT is held low before start-up it will prevent switching and simply stay in the UVLO reset cycle (which is what you are seeing on VDD). 
Other fault possibilities are in Table 7-4, which are all those where "Delay to Action" = "none".   

From Table 7-4, we have ruled out "P13 pin open".  For the remainder, please check:
1.  XCD pins are connected to AGND;
2.  RDM and RTZ resistor values on the board match the values on the schematic, and are connected to the controller pins.

In Table 7-4, there is also the "CS pin short" fault, but this fault requires a single pulse on PWML (and RUN also goes high for this pulse).
This fault is the reason that the EVM starts at ~100V.  As discussed below the Table 7-4, in Section 7.4.13.1, Vcs must reach 0.2V within 2us on the first pulse or a fault is assumed.  Using V/L = di/dt, with the EVM inductance of 160uH and Rcs = 0.1662R, Vbulk must be > 160uH*(0.2V/0.1662R)/2us = 96.3V to meet the <2us criterion to avoid shutdown from "CS pin short" fault.    

For your 460uH substitute transformer, it will take 3x higher Vin to start-up, unless you also increase Rcs value to compensate.  
I suspect that this is why your board will not start up.  But you had said that you see no gate-drive or RUN pulses, so that's why I recommend above that you verify that first.  You may be missing them, because the "CS pin short" fault also keeps the UVLO cycling for 1.5 seconds before allowing another attempt at switching.  At slow sweep, it is easy to miss a single 2us pulse repeating only every 1.5s.     

Regards,
Ulrich

Hello Ulrich,

The duration before it starts to shut off did increase after i added VDD capacitance, but that does not help with the main issue - low secondary voltage.

Optocoupler collector voltage looks stable, no swinging during Vout swinging.

I am trying a different off the shelf transformer and QLSRC does not ring as much, not sure if its because how i mounted it since the footprint is different or if its just "better".

With the first transformer (https://www.we-online.com/components/products/datasheet/7508112514.pdf) i had around 13V sec and 8V aux output. 

Now with the second transformer (https://www.we-online.com/components/products/datasheet/7508112330.pdf) i am seeing around 6.5V sec and 8V aux. 

So, the Nsa makes sense. What does not make sense is why am i getting such low Sec output voltage even if i tried adjusting R31, R25, R26, R9. Only R9 seems to make a small difference but barely any. I have R31 = 10k and R25 = 150k, so i would expect few times higher Vout than what i am seeing. Vout does not change with different Vin, only the ripple and audible sound seems to be affected.

Kindly,

Valentinas

Hello Ulrich,

Since the board was hand mounted, i decided to build one more. At first i had other issues but those turned out to be soldering errors. Eventually it started to progress, now i am seeing output for 160ms, then it goes off.

Btw regarding TLV being 1.24V, you are correct, but i actually have TL431, which does have 2.5V ref. Its a graphical error in the schematics.

Regarding gate being able to handle only 20V. i did realize that and patched in a 10V zener + 100R to limit current, so my gate driver is protected. Forgot to tell you about this.

So, as i mentioned, im now seeing a nice output for 160ms, then it goes low. Repeats after 1.5s (restart happens).

21.5V AUX

33V Vout

3V Vvs (Rvs2 i have 3.3k instead of 6 98k as in EVM).

It cannot be Vovp because it goes up to just 3V, no overshoot. So, the next possible scenario is Vopp. What do i measure and calculate for this? Currently i have EVM value 402R for Ropp. 

What i find strange is that Vout is not easy to adjust, i am not able to reduce it slightly, it makes no difference if i change R25 and R31 but if i make a big enough jump, it just drops Vout to like 25V which is then too low for Vaux to take over VDD. I probably need to adjust other resistors, but i did not have the time yet to read through. Do you have a hint? Too large R25 R31 values maybe?

Thanks for the help,

Valentinas

Hi Ulrich,

You were right about the feedback loop. I made a mistake by placing the gate 10V zener on the common net as for the TL431 so its reference was being fed 10V constantly. I fixed this patching error and now im getting the programmed voltage. It was causing the over-power protection. 

At higher Vin it goes into OPP mode but if i adjust the Rcs, it allows me to increase the Vin. 

I wont receive my 900V supply until a few weeks from now but i will get something close to it in the meantime. 

Now im thinking - i will need to a add over 30V of series zeners to drop the excess of 68V from TL431.

I want to calculate my OPP setting but the formula asks for td(cst) input and i dont know what its equal to. Is it a standard or varying value?

Have you made any calculations will it work at 30W with my 10mH transformer at 650-900Vin and 68Vout?

Thanks for your patience!

Valentinas 

Hi Valentinas, 

It's good to see some real progress. 

I have not made any calculations yet, but your question makes me wonder what the actual design targets are. 
Previously, we were shooting for 15V, then 40V, now 68V.  The documents above refer to 600mA output, now Pout = 30W which means Iout = 440mA.
Startup was 100V trying for 50V, now input appears to be 650-900Vdc.  

Before doing many more calculations, I'd like a list of the actual design targets for input and output, including special cases and limitations and desired start-up voltage. 

Here are some issues that I find, with the information available so far:
1.  800-V rating of CPC3982 will not do well with 900V input plus reflected voltage on primary. 
2.  Transformer design 750371607 (10mH) has Nps ratio of 20:1, so reflected voltage = 1360V at Vout = 68V.   That ratio is good for a low voltage on the SR FET Q3, but bad for the stress on the primary FET Q1.   Also dielectric rating from xfmr pin 1 to pin 6 (1000VAC) is inadequate for the peak voltage expected  between these windings.  
3.  D9 will not survive with 1360V reflected back.  Neither will D2, but D2 is not necessary.  
4.  I noticed that the AUX winding polarity in the schematic diagram is backwards.  Pin 5 should go to HV_GND.

For the Rcs equation (17), td(cst) is described in the paragraph just below the equation as a summation of a few different delays.  Of these, td(cs) is specified in the Electrical Characteristics table (page 8), you don't have a low-side driver, and CS filter and Coss delays must be estimated.   It is too soon to be too accurate about this calculation.  Since a SiC FET has fairly low Coss, an educated guess would be to use td(cst) = 75ns total.  

I wonder if the transformer design needs to be rethought, which will involve making trade-offs with the semiconductor ratings.  
Please note: I am going to be out-of-office this coming Monday.  If someone else covers this thread, they may need a lot of time to come up to speed on the issues. 

Regards,
Ulrich

Hi Ulrich,

Sorry for the confusion.

The final design will have:

650-900Vin

68Vout/600mA

The reason i have been changing things one by one is to understand how everything works and the dependencies. I want to slowly get to the final design.

I understand about the possible overshoot issues, but that can be solved.

Right now we are stressing about locking the transformer design so it can go for a small volume production because we will need that ready this summer.

Now I have connected the 10mH transformer and its not doing what I expect it to. I also have a 4mH version so i might try that.

Vin 165V. Yellow Vout. Pink Vaux. Blue Vrcs (Rcs = 2.2R). Keeps doing that every 1.5s.

I am still early into this investigation but Vout looks very low. I am really confused about this. Any tips here?

Thanks,

Valentinas

Hi Valentinas, 

We have reviewed this issue before.  This is a recurring start-up fault because your Vin is too low to overcome the "CS-short" fault time limit of 2us. 
Vcst(sm1) threshold = 0.2V/2.2R = 0.909Apk.  With Lm = 10mH, tON to reach 91mA = 0.01*0.091/165 = 5.5us. 
You'll need Vin > 455V to overcome this fault.  

For lower Vin start, you can overcome that using 6.8R+ at Rcs, but you won't get full power.  It would seem to be worth testing though, to get past this hurdle and see what's next.  However...

Your statement about "...possible overshoot issues..." concerns me that what I'm trying to convey is not being understood.
I'm not talking about mere overshoots, I'm warning that your primary circuit will experience exceptionally high sustained voltages for a few cycles before it blows up.  These are not overshoots or transients that can be clamped or snubbed out.  
Most of this stress comes from the 20:1 Pri:Sec turns ratio.
I think the transformer definitely needs a redesign. 

Your comment about trying a 4mH option also raises concern.  You've been making changes one-by-one to understand dependencies.  I've been trying to show that this design has many interdependencies, where changing one parameter often requires changing more than one other parameters to accommodate the effects of the first change.  This is an extremely slow way to get to the final design, and in my opinion not likely to improve understanding of what's going on.  Or, of what should go on.  We haven't even gotten to what I anticipate to be the real problems to be solved once the design is mostly settled, such as how well the ZVS works, actual vs. expected efficiency, and possible self-interference from di/dt's and dv/dt's, for example.   

Making calculations for the final design up front will tell you what practicable tradeoffs will have to be made in the component selection, since primary FET ratings and availability are limited.  And it will avoid acquiring the false notion that something easily done at low voltages will be just as easy to accomplish at 900V.   

Regards,
Ulrich

Hello Ulrich,

I made the test board work with 460uH and 800uH off the shelf transformers, but i am having troubles with 4mH, 10mH. 

In the picture above you can see the blue line (Vrcs) is high enough for the controller to start but the signal is not stable.

In the picture below the blue line is a 460uH transformer which i have no problems with, but the 4mH transformer (Vrcs red, 500mV/div) looks completely wrong.
After lots of Rcs adjustment and voltage increase i can make it try to turn on but immediately it starts to produce huge spikes >1.2V which is basically the red graph, which makes it trigger Vocp. I am already at 0.44R @320V so if i reduce Rcs to 0.4R then it wont start at all @320V. If i just increase the voltage to around 335V then it starts and immediately triggers overcurrent protection.

I tried various Ccs capacitances (300p,1n,1.5n, 2.2n, 3.3n, 4,7n, 6.8n, 10n). At 2.2n it doesnt even reach minimum Vcs, at 1.5n tries to start but as soon as it starts to switch the Vcs goes so 3V, due to inductances.

It looks like the transformer with high inductance (+high leakage and interwinding capacitance) cannot be used with this IC or it will keep triggering overcurrent.

Below is the Lm calculation. What happens if the transformer has 1mH under same voltage/current conditions? Will it just try to increase the frequency? So basically in this calculator we can enter say 900kHz which gives us a calculated 1mH recommendation and everything will work just fine?
 

I suppose EMI is much worse at higher frequencies? Or maybe its easier to solve because smaller EMI filters are needed?

Thank you!

Valentinas

Hello Ulrich,

An off the shelf transformer with lower inductance seems to work well. We will use it for the low voltage isolated conversion.

Now i need to make this work with my 4mH transformer for HV isolated conversion.

Below blue is Vcs and yellow is Vout. I need around 40V there for Vaux to get enough voltage to keep it alive.

If i adjust TL431 resistors, its pin1 changes but Vout does not.

If i reduce optocoupler resistors, TL431 pin1 goes up but Vout does not change. Currently i have 510R at R32. Tried various R26 values - how is it calculated exactly? On my LV converter i had to reduce is to 11k to make it work.

I am using 0.5Rcs and it starts to "try to switch" at around 530V. At higher Rcs it did not even reach 26.8V, but it looked like it was OPP triggering.

This repeats every 1.5s.

Vcs does not go above 1.2V, so why does Vout stop increasing?

Vvs goes to 2V by the time Vout reaches 26.8V

FLT is at 2.4V.

Any ideas?

I will order the version without OPP and see if this solves the problem.

Kindly,

Valentinas

Hello Valentinas, 

Vout stops rising because the switching stops. 
An OPP fault is characterized having peak Vcs pulses (not including leading-edge spikes) that continuously exceed the Vcst(opp) level (see Figure 7-43 in datasheet) for a duration that exceeds160ms.  
The screen shot shows some pulses with diminishing peaks that last about 0.5ms.  This does not constitute an OPP fault. 
Some other fault which involves a 1.5s shutdown time must be causing it.  

Please review the Fault Protection Tables 7-3 and 7-4 to identify the possible faults which match the timings and investigate for symptoms of each possibility to eliminate those faults that don't match the symptoms listed.
Note: the IC acts on signals that it sees at its input pins, not on what is out in the power stage.
If the signal levels at the pins point to an OVP shutdown (for example) even though Vout is no where near OVP level, then look for errors in VS divider resistances and/or turns ratio.  

Never assume that the pcb assembly is exactly equal to the schematic diagram.  
Many times, the schematic is fine but errors were made in constructing the board. 

That said, the behavior in your latest screen shot is curious.  
Normally during start-up, peak current goes high and stays high until Vout approaches its target level.  
This is because the TL431 normally stays off (Vka roughly tracks Vout going up) until the feedback reaches the REF level. 

In this case the current peaks are diminishing, which means Vcst is reducing as Vout rises, which implies that current is increasing in the opto-coupler photodiode.  Higher diode current means higher collector current which is higher FB current which reduces Vcst.  
So regardless of what is shutting off the switching, the reduction if Ipeak is a symptom of another problem which indicates that something in the TL431 block is not working right.  

As I mentioned before, the TL431 Vka is limited to < 37V, so a clamp is needed on the voltage at R26 to avoid damaging the TL431.  
You had mentioned that you made modifications in this area to limit VDD stress on the isolator. 
I have not seen an updated schematic diagram since your first post, so there may be some error in the modification or on the pcb.  

Regards,
Ulrich

Hello Valentinas, 

I've seen no correspondence on this E2E thread in about 2 weeks.  
If you have solved the problem, then I'd like to close this thread.  

Regards,

Ulrich

Hello Ulrich,

The thread can be closed, although i have not suceeded in making it work with a 4mH transformer. It did work with some off the shelf 800uH, which indicates that most likely the parasitics was the cause.

We did not have the time to troubleshoot it further so we went with UCC28C56H which has worked with the 4mH transformer.

UCC28781 works with our low voltage design so we will still use this IC there.

Thank you for now.

Valentinas