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Original question:

TPS7H1101A-SP: Parallel configuration

TPS7H1101A-SP: Parallel configuration info request

Filipe Costa
Prodigy 60 points
Part Number: TPS7H1101A-SP

Is there further information available about the parallel operation?
Is there an excel sheet version of TPS7H1101A_DesignCalculator.xlsx configured for parallel operation?
I am struggling to understand how to select RCL for the current limitation.
I would like to set the current limit to 4A (2A per LDO) and to have Foldback enabled.

Thanks in advance,
Filipe

  • 0
    TI__Guru 62930 points

    Filipe,

    There is not an excel calculator that will help with this.   I will consider adding another tab to the current calculator to help with this in the future.

    Unfortunately, I do not believe it is possible to operate a parallel configuration with foldback mode. 

    Essentially in the parallel configuration, both LDOs are continually operating at a current limit.  The Ics current from one LDO is defining the current limit via Ipcl of the other LDO and vice versa.  In this manner, they share current very well.

    I have not worked through the current limiting with a parallel configuration.  So, I would like to discuss my analysis with the designer to make sure I am not missing anything.

    I will do some additional research and get back to you in 1-2 days.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 60 points

    Wade,

    Thank you for your prompt reply. I will wait for further information from your side. 

    Best regards, 
    Filipe Costa 

  • 0 in reply to Filipe Costa
    TI__Guru 62930 points

    Filipe,

    Just wanted to let you know this is still an active request. Unfortunately need a little more time to get feedback from design team.

    I will update as soon as I have the information. 

    Thanks.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 60 points

    Hi Wade,

    No worries. Thank you for keeping me updated.

    Best regards,
    Filipe Costa

  • 0 in reply to Filipe Costa
    TI__Guru 62930 points

    Filipe,

    I was able to do some experimentation to help understand this a little better.

    First off, foldback mode is not possible with a parallel config.  This is due to the PCL pin being the source for driving the current through Rcl.  PCL has a source for the current that is Vfb, so with no current load that implies that Vcs max voltage will be Vfb ~0.605mV.  Thus, as devices are loaded, the voltage on the CS pin will drop from this max value.

    The threshold for disabling foldback and going into constant current mode is ~90% of Vfb, so ~544mV.   So, it is not possible to operate in this narrow region.  Additionally, there would be sharing issues with one or the other going into foldback while the other did not.

    With respect to the current limiting with the parallel config.  Essentially the current limit is triggered when Vcs can no longer sink additional current due to it not being properly biased any longer, and its voltage being less than ~300mV.

    This is somewhat convenient, as this 300mV can be considered 1/2 of Vfb.

    The two effectively parallel Rcl resistors will become 1/2 Rcl.   The two 1/2s cancel in the equations, and the equation for current limiting the parallel config is effectively the same as a single unit.  Hopefully this makes sense.

    Using the TPS7H1101A_Calculator, I tested a configuration with 7.13k ohm Rcl on each leg.

    The calculator shows min Ilim of 3.86, 4.45, and 5.56A (min, nom, max)

    Testing the configuration showed it to current limit at almost exactly 4A.

    The voltage at which the CS pin can no longer sink additional current is not a specified parameter.  Thus, it would be wise to have some margin, and characterize the system to insure operation as expected across environmental conditions.

    If this answers your question, please click this resolved my question.
    Regards,
    Wade