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BQ76952: Gate Driver Connection Between CHG and DSG Pins

Yunus Emre Üzmez
Prodigy 20 points
Part Number: BQ76952

Hi,

I want to use BQ76952 in my project. Battery voltage is 48V. In this project i am going to use gate driver.My concern is, BQ76952 uses charge-pump technology so,CHG DSG pins will have a battery voltage+5/10V voltage. (5V or 10V can be selected with registers). But gate driver input pins are capable of maximum 20V. 

  • Can I disable charge pump and use DSG-CHG as an logic level pins? (I have researched that and I don't think it is possible but I want to ask either)
  • I think about analog circuits to accomplish that (opamp comparator, resistor divider etc.) but I couldn't find any suitable circuit for that. Do you have any idea for that?

  • I have examined TIDA-0102216 refence design.  In this reference TI used gate driver. Gate driver charge control signal comes from BQ76952 DCHG and gate driver discharge control signal comes from DDSG. I didn't understand how this configuration works as an DSG and CHG pins. For example if there is short circuit will DDSG be low? The circuit scheme that i talk about is here. And i just found the two explanations of DDSG, DDCHG working with CHG and DSG. I will appreciate if you share any documents about that situation.

Here is a explanation : 

 

Reference design gate driver and control signals: 

Thank you. 

  • 0
    TI__Expert 3245 points

    Hi Yunus, 

    You are correct that the DSG and CHG pins cannot be used as logic level pins. In theory this could be done with additional circuitry but we unfortunately do not have any examples to refer to. This would ultimately add another level of complexity to your design.

    If you are not planning on using the high-side NFET drivers then the charge pump can be disabled by clearing the Settings:FET:Chg Pump Control[CPEN] and Settings:FET:FET Options[FET_CTRL_EN] configuration bits. 

    Fortunately, the DDSG and DCHG bits are included in our device with low-side applications in mind and are able to be configured as logic level pins to fit your requirements. Please refer to section 6.7 DDSG and DCHG Pin Operation of the TRM for a more in-depth explanation. 

    Hope this helps!

    Best, 

    -Luis Torres