BQ76952: Is the PDSG pin leakage known for the BQ76952 at high temperature ?

Hello Harry,

The PDSG pin would not be sinking any current when the PDSG FET is disabled, it is in a tristate mode, so the gate is pulled to high by the 1-MOhm resistor. We tested and characterized the PDSG driver using a 10-MOhm driver and never saw false turn-ons.

In what conditions do you see false turn-on? What is the battery voltage? How long does the FET remain ON? Do you have any captures? In the case of the the previous E2E posted, they only saw this event after conformal coating.

The Zener (D6) I don't believe is really needed. This is the only component I can see that may be causing a false turn-on. If it is removed do you still see a false turn-on?

Best Regards,

Luis Hernandez Salomon

Thanks for the detail and suggestions, Luis.

I am embarrassed that I posted in haste and the issue was unrelated to the PDSG FET circuit.

Having worked through this and for the thread, would you explain why the protection zener is not needed ?

I have seen the zener on the reference designs and my approach has been to consider ways the BQ76952 can be damaged that prevent the final protection; driving the chemifuse open.

Is RG1 sufficient to limit current into the BQ if a surge at the PACK pin destroys PDSG1 and creates a path to the PDSG pin ?

I am testing continuous reverse pack voltage protection now and next is positive and negative surges at the PACK pins. The forward voltage of the zener also protects the pin from transients below Vss but if the pin can sustain damage without compromising the rest of the BQ functions then I can remove it.

Thanks once again and all the best
Harry

Hello Harry,

No worries! Things happen.

I gave some more thought, my initial though was that it was unlikely that the voltage here would exceed the ABS MAX. However, after more thinking I believe it could be possible for this voltage to be exceeded if the PDSG FET is disabled (85-V ABS MAX), as the PDSG pin would be in a tristate state, so the voltage at the pin is pulled to the common-drain voltage. 

If you believe that your transients will not exceed this voltage, then this should be okay. This is probably why they added it in the reference design.

My only concern would be that if the Zener were to slightly turn-on or turn-on, it would cause enough leakage causing an unintentional turn-on.

Best Regards,

Luis Hernandez Salomon

Thanks Luis

I am considering positive transients although sluaad4.pdf was really helpful in showing (without warranty) that the pins were observed to survive 120V transients.

My core consideration is negative going transients and I asked in a thread some time ago about the current that pins can source when transients drive them below Vss:

e2e.ti.com/.../bq76952-maximum-pin-currents-into-body-diodes

The drive and negative protection circuit for DSG pin in that thread is working well although I now have two parallel 10K 1/2W resistors at R95.

With -42V applied on a 10S pack (main FETs off so far) I see 200mV across R44 (5.1k) so 40uA DSG pin current which I assume will not stress the BQ. Thinking this through is the reason for my earlier pin current questions.

The design we have has a bidirectional TVS to see if we can achieve continuous reverse pack voltage protection. But that requires reverse voltage protection to respond to negative transients to the TVS clamping voltage; Vc @ Ipp (10uS/1000uS) +/-77.4V and Vc @ Ipp (8uS/20uS) +/-100V for the 10S assembly variant of the BMS.  

For now I will leave the zener footprint on the board and I have the option not to place it as we think and test further.

But on your final comment, I was wondering if Shyama's zener choice might have unexpected leakage or too low zener voltage starts conducting and only needs slightly more leakage from the conformal coating. He doesn't say but hopefully confirmed the source.

I will the thread open in case you have a further comment but it can be set resolved.

All the best
Harry