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TPS70345PWP enable pin

Sarmad Abedin
Intellectual 900 points

 We have setup the TPS70345 device so that the Enable pin is tied Low. Is there any potential issues we might see by keeping this device enabled as the input source ramps up?

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    TI__Guru**** 166136 points

    Once VINx > UVLO voltage, the regulators will turn on their respective FETs hard to charge the output capacitors.  You will see inrush current through each regulator roughly equal to the current limit of each regulator.  Note that this would happen even if you used /EN to enable the device.

    The main issue I see is imprecise turn on/off time of each regulator because you are relying on the UVLO trip voltage which has some variation.  This could result in the regulators not starting up in the sequence you intend per the SEQ pin because each rail has a different UVLO comparator and therefore slightly different trip point.