Hi,
we're in the process of designing the TPS23751 into a new PoE powered system. We've played around with the EVM and are happy with the performance and features of the IC, but we only really need about 6W.
This puts us down at the switch-over point between PWM and VFO mode, and thus the point at which the circuit goes from synchronous to diode rectification to improve the losses at lower power.
While we've tracked out the design for synchronous rectification, we've also added the diode rectifier, and are likely to go that route because we're not really going to need the improved efficiency of synchronous rectification at higher powers...it will also be a bit more cost effective.
- We were wondering what the implications are for increasing the resistance of the current sense resistor?
- We assume that this would have the effect of reducing the maximum output current, and thus lower the current limit...is our assumption correct?
- Might there also be a knock-on effect for the slope compensation?
The datasheet doesn't really help with this aspect of the design process, merely suggesting that you stick to the reference design.
Any TI staff who can help with this?
Cheers,
Chris
